PS002603-0108
Z86L98ZEM
Product Specification
7
same values in the general-purpose registers, while the real device has random or
undefined values.
10. Power supply ramp-up/rise time must be set so that when the minimum power-on
reset time (Toper) expires, the V
CC
i s i n t h e s p e c i f i e d o p e r a t i n g r a n g e o f t h e d e v i c e .
11. If the Program Counter jumps to an unknown address:
(a) Stack is not set to internal. Register %F8(P01M Reg) bit D2 are not set to
State1.
(b) The Stack Pointer Register %FE(SPH) and Register %FF(SPL) are not initial-
ized. For the internal Stack, SPH does not have to be initialized because it is not
used. The SPH and SPL are reset to 00H after any reset or Stop-Mode Recov-
ery.
(c) An instruction other than DI was used to disable interrupts.
(d) The Stack overflowed into the general-purpose register locations.
(e) When making changes to the IMR register, GLOBAL interrupts must be dis-
abled before using a DI instruction.
12. If the Program keeps resetting:
(a) Program Counter rolled over from value FFFF to 0000 and proceeded back to
the beginning of program.
(b) Watch-Dog Timer (WDT) was not refreshed from devices with the WDT fea-
ture.
The emulator must not be started with an OTP device or Adapter in the programming
socket, because the emulator might not start-up correctly.
A shorted PLCC or DIP OTP can crash the emulator when inserted into the OTP pro-
gramming socket. If a PLCC part is inserted and causes a temporary short, then the part
loses its functions. An attempt to perform BLANK CHECK on such a part causes the
h o u r - g l a s s t o a p p e a r c o n t i n u o u s l y . T h e W i n d o w s a p p l i c a t i o n m u s t b e r e s e t a n d r e s t a r t e d .
13. The bits of non-implemented features for devices having PC ON register must be set
to State1 on the emulator.
14. When interrupts are enabled, setting a breakpoint after a Halt instruction, breaks the
emulator at the first instruction in the interrupt service routine that is serviced when
an IRQ occurs.
15. SCLK/16 Mode of SMR register is not supported.
16. The OTP activity bar is not proportionate to the address being processed.
Note:
Caution:
