OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

DG401DY

P1-P3P4-P6P7-P9P10-P12
1
®
FN3284.11
DG401, DG403
Monolithic CMOS Analog Switches
The DG401 and DG403 monolithic CMOS analog switches
have TTL and CMOS compatible digital inputs.
These switches feature low analog ON resistance (<45Ω)
and fast switch time (t
ON
<150ns). Low charge injection
simplifies sample and hold applications.
The improvements in the DG401, DG403 series are made
possible by using a high voltage silicon-gate process. An
epitaxial layer prevents the latch-up associated with older
CMOS technologies. The 44V maximum voltage range
permits controlling 30V
P-P
signals. Power supplies may be
single-ended from +5V to +34V, or split from ±5V to ±17V.
The analog switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with analog
signals is quite low over a ±15V analog input range. The three
different devices provide the equivalent of two SPST (DG401)
or two SPDT (DG403) relay switch contacts with CMOS or
TTL level activation. The pinout is similar, permitting a
standard layout to be used, choosing the switch function as
needed.
Pinouts
DG401
(16 LD SOIC, TSSOP)
TOP VIEW
DG403
(16 LD SOIC, TSSOP)
TOP VIEW
NOTE: (NC) No Connection.
Features
• ON Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . . 45Ω
• Low Power Consumption (P
D
). . . . . . . . . . . . . . . . . . .<35μW
• Fast Switching Action
-t
ON
(Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns
-t
OFF
(Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns
• Low Charge Injection
• DG401 Dual SPST; Same Pinout as HI-5041
• DG403 Dual SPDT; DG190, IH5043, IH5151, HI-5051
• TTL, CMOS Compatible
• Single or Split Supply Operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Audio Switching
• Battery Operated Systems
• Data Acquisition
• Hi-Rel Systems
• Sample and Hold Circuits
• Communication Systems
• Automatic Test Equipment
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
D
1
NC
NC
NC
NC
NC
D
2
NC
S
1
V-
GND
V
L
V+
IN
2
S
2
IN
1
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
D
1
NC
D
3
S
3
S
4
D
4
D
2
NC
S
1
V-
GND
V
L
V+
IN
2
S
2
IN
1
Ordering Information
PART
NUMBER*
PART
MARKING
TEMP.
RANGE (°C) PACKAGE
PKG.
DWG. #
DG401DY* DG401DY -40 to +85 16 Ld SOIC M16.15
DG401DYZ*
(Note)
DG401DYZ -40 to +85 16 Ld SOIC
(Pb-free)
M16.15
DG401DVZ*
(Note)
DG401 DVZ -40 to +85 16 Ld TSSOP
(Pb-free)
M16.173
DG403DY* DG403DY -40 to +85 16 Ld SOIC M16.15
DG403DYZ*
(Note)
DG403DYZ -40 to +85 16 Ld SOIC
(Pb-free)
M16.15
DG403DVZ*
(Note)
DG403 DVZ -40 to +85 16 Ld TSSOP
(Pb-free)
M16.173
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Data Sheet November 20, 2006
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 1999, 2002-2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
FN3284.11
November 20, 2006
Schematic Diagram
TRUTH TABLE
LOGIC
DG401 DG403
SWITCH SWITCH 1, 2 SWITCH 3, 4
0OFF OFF ON
1ON ON OFF
NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V.
Functional Diagrams
DG401 DG403
SWITCHES SHOWN FOR LOGIC “1” INPUT
15
10
9
16
8
1
S
1
IN
1
IN
2
S
2
D
1
D
2
V
L
V+
GND V-
12 11
13 14
15
10
9
4
16
5
8
3
1
6
S
1
S
3
IN
1
IN
2
S
2
S
4
D
1
D
3
D
2
D
4
V
L
V+
GND V-
12 11
13 14
V-
V+
V+
V
L
V
IN
GND
V-
DRAIN
SOURCE
3
FN3284.11
November 20, 2006
Absolute Maximum Ratings Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
V
L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V+) +0.3V
Digital Inputs V
S
, V
D
(Note 1) . . . . . (V-) -2V to (V+) + 2V or 30mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle, Max). . 100mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max)
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max)
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min)
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20ns
Thermal Resistance (Typical, Note 2) θ
JA
(°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(SOIC and TSSOP- Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on S
X
, D
X
, or IN
X
exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, V
IN
= 2.4V, 0.8V (Note 3), V
L
= 5V,
Unless Otherwise Specified
PARAMETER TEST CONDITIONS
TEMP
(°C)
(NOTE 4)
MIN
(NOTE 5)
TYP
(NOTE 4)
MAX UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
ON
R
L
= 300Ω, C
L
= 35pF +25 - 100 150 ns
Turn-OFF Time, t
OFF
+25 - 60 100 ns
Break-Before-Make Time Delay (DG403), t
D
R
L
= 300Ω, C
L
= 35pF +25 5 12 - ns
Charge Injection, Q (Figure 3) C
L
= 10nF, V
G
= 0V, R
G
= 0Ω +25 - 60 - pC
OFF Isolation (Figure 4) R
L
= 100Ω, C
L
= 5pF, f = 1MHz +25 - 72 - dB
Crosstalk (Channel-to-Channel) (Figure 6) +25 - -90 - dB
Source OFF Capacitance, C
S(OFF)
f = 1MHz, V
S
= V
D
= 0V (Figure 7) +25 - 12 - pF
Drain OFF Capacitance, C
D(OFF)
+25 - 12 - pF
Channel ON Capacitance, C
D(ON)
+ C
S(ON)
+25 - 39 - pF
DIGITAL INPUT CHARACTERISTICS
Input Current with V
IN
Low, I
IL
V
IN
Under Test = 0.8V, All Others = 2.4V Full -1 0.005 1 μA
Input Current with V
IN
High, I
IH
V
IN
Under Test = 2.4V, All Others = 0.8V Full -1 0.005 1 μA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full -15 - 15 V
Drain-Source ON Resistance, r
DS(ON)
V+ = 13.5V, V- = -13.5V,
I
S
= 10mA, V
D
= ±10V
+25 - 20 45 Ω
Full - - 55 Ω
r
DS(ON)
Matching Between Channels, Δr
DS(ON)
V+ = 16.5V, V- = -16.5V,
I
S
= -10mA, V
D
= 5, 0, -5V
+25 - 3 3 Ω
Full - - 5 Ω
Source OFF Leakage Current, I
S(OFF)
V+ = 16.5V, V- = -16.5
V
D
= ±15.5V, V
S
= 15.5V
+25 -0.5 -0.01 0.5 nA
Full -5 - 5 nA
Drain OFF Leakage Current, I
D(OFF)
+25 -0.5 -0.01 0.5 nA
Full -5 - 5 nA
Channel ON Leakage Current, I
D(ON)
+I
S(ON)
V± = ±16.5V, V
D
= V
S
= ±15.5V +25 -1 -0.04 1 nA
Full -10 - 10 nA
P1-P3P4-P6P7-P9P10-P12

DG401DY

Mfr. #:
Buy DG401DY
Manufacturer:
Maxim Integrated
Description:
Analog Switch ICs Dual High-Speed SPST CMOS Normally Open
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet