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DG401DVZ-T

P1-P3P4-P6P7-P9P10-P12
4
FN3284.11
November 20, 2006
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 16.5V, V- = -16.5V,
V
IN
= 0V or 5V
+25 - 0.01 1 μA
Full - - 5 μA
Negative Supply Current, I- +25 -1 -0.01 - μA
Full -5 - - μA
Logic Supply Current, I
L
+25 - 0.01 1 μA
Full - - 5 μA
Ground Current, I
GND
+25 -1 -0.01 - μA
Full -5 - - μA
NOTES:
3. V
IN
= input voltage to perform proper function.
4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, V
IN
= 2.4V, 0.8V (Note 3), V
L
= 5V,
Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS
TEMP
(°C)
(NOTE 4)
MIN
(NOTE 5)
TYP
(NOTE 4)
MAX UNITS
Test Circuits and Waveforms
NOTES:
6. Logic input waveform is inverted for switches that have the
opposite logic sense.
7. V
S
= 10V for t
ON
, V
S
= -10V for t
OFF
.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for IN
2
and S
2
.
For load conditions, see Specifications. C
L
includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
50%
t
r
< 20ns
t
f
< 20ns
t
OFF
90%
3V
0V
V
S
0V
t
ON
V
O
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
-V
S
SWITCH
INPUT
10%
(NOTE 7)
V
O
V
S
R
L
R
L
r
DS ON()
+
------------------------------------
=
SWITCH
INPUT
LOGIC
INPUT
S
1
IN
1
V+
D
1
R
L
C
L
V
O
GND
V-
V
L
0V -15V
5V +15V
R
L
= 300Ω
C
L
= 35pF
5
FN3284.11
November 20, 2006
FIGURE 2A. MEASUREMENT POINTS
C
L
includes fixture and stray capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2. BREAK-BEFORE-MAKE TIME
FIGURE 3A. MEASUREMENT POINTS FIGURE 3B. TEST CIRCUIT
FIGURE 3. CHARGE INJECTION
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. INSERTION LOSS TEST CIRCUIT
Test Circuits and Waveforms (Continued)
90%
3V
0V
t
D
0V
LOGIC
INPUT
SWITCH
OUTPUT
SWITCH
OUTPUT
V
S1
V
S2
90%
t
D
0V
(V
O1
)
(V
O2
)
LOGIC
INPUT
V
S1
= 10V
IN
1
V+
D
1
R
L1
C
L1
V
O1
GND
V-
V
L
0V -15V
5V +15V
R
L
= 300Ω
C
L
= 35pF
D
2
R
L2
C
L2
V
O2
V
S2
= 10V
V
O
ΔV
O
IN
X
ON
OFF
ON
Q = ΔV
O
x C
L
SWITCH
OUTPUT
V+
D
1
C
L
V
O
V-
R
G
V
G
V
L
0V -15V
5V +15V
GND
ANALYZER
R
L
+15V
SIGNAL
GENERATOR
V+
C
V-
-15V
C
0V, 2.4V
V
S
V
D
IN
X
GND
+5V
V
L
C
ANALYZER
R
L
+15V
SIGNAL
GENERATOR
V+
C
V-
-15V
C
0V, 2.4V
V
S
V
D
IN
X
GND
+5V
V
L
C
6
FN3284.11
November 20, 2006
Application Information
Dual Slope Integrators
The DG403 is well suited to configure a selectable slope
integrator. One control signal selects the timing capacitor C
1
or C
2
. Another one selects e
IN
or discharges the capacitor in
preparation for the next integration cycle.
Peak Detector
A
3
acting as a comparator provides the logic drive for
operating SW
1
. The output of A
2
is fed back to A
3
and
compared to the analog input e
IN
. If e
IN
> e
OUT
the output of
A
3
is high keeping SW
1
closed. This allows C
1
to charge up
to the analog input voltage. When e
IN
goes below e
OUT
, A
3
goes negative, turning SW
1
off. The system will therefore
store the most positive analog input experienced.
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCES TEST CIRCUIT
Test Circuits and Waveforms (Continued)
0V, 2.4V
ANALYZER
+15V
V+
C
V
S1
SIGNAL
GENERATOR
R
L
GND
IN
1
V
D1
IN
2
50Ω
0V, 2.4V
NC
V-
-15V
C
V
D2
+5V
V
L
C
V
S2
+15V
V+
C
GND
V
S
V
D
IN
X
V-
-15V
C
IMPEDANCE
ANALYZER
0V, 2.4V
+5V
V
L
C
AS REQUIRED
V-
GND
-15V
IN
2
IN
1
S
3
S
1
S
2
S
4
D
1
D
2
D
3
D
4
+15V+5V
V
L
V+
DG403
C
1
C
2
e
OUT
e
IN
INTEGRATE/
SCOPE
TTL
RESET
SELECT
FIGURE 8. DUAL SLOPE INTEGRATOR
e
OUT
e
IN
C
1
R
1
SW
2
SW
1
RESET
+
-
+
-
+
-
DG401
A
1
A
3
FIGURE 9. POSITIVE PEAK DETECTOR
A
2
P1-P3P4-P6P7-P9P10-P12

DG401DVZ-T

Mfr. #:
Buy DG401DVZ-T
Manufacturer:
Renesas / Intersil
Description:
Analog Switch ICs SWITCH 2X SPST IND
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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