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MAX9157EHJ+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
MAX9157
matching the differential impedance of the bus (taking
into account any reduced impedance due to loading).
Traces, Cables, and Connectors
The characteristics of input and output connections
affect the performance of the MAX9157. Use con-
trolled-impedance traces, cables, and connectors with
matched characteristic impedance.
Ensure that noise couples as common mode by run-
ning the traces of a differential pair close together.
Reduce within-pair skew by matching the electrical
length of the traces of a differential pair. Excessive
skew can result in a degradation of magnetic field can-
cellation. Maintain the distance between traces of a dif-
ferential pair to avoid discontinuities in differential
impedance. Minimize the number of vias to further pre-
vent impedance discontinuities.
Avoid the use of unbalanced cables, such as ribbon
cable. Balanced cables, such as twisted pair, offer
superior signal quality and tend to generate less EMI
due to canceling effects. Balanced cables tend to pick
up noise as common mode, which is rejected by the
receiver.
Board Layout
A four-layer PC board that provides separate power,
ground, input, and output signals is recommended.
Keep the LVTTL/LVCMOS and BLVDS signals separat-
ed to prevent coupling.
Quad Bus LVDS Transceiver
10 ______________________________________________________________________________________
INPUTS OUTPUTS
RE_ V
ID
= (V
DO_+
/R
IN_+
) - (V
DO_-
/R
IN_-
) RO_
LV
ID
< -100mV L
LV
ID
> 100mV H
L
Fail-safe operation guaranteed when
DO_+/RIN_+ and DO_-/RIN_- are
open, undriven and shorted, or
undriven and parallel terminated
H
HX Z
Table 3. Receiver Mode
PIN INTERNAL RESISTOR
DE12 Pulldown to GND
DE34 Pulldown to GND
RE12 Pullup to V
CC
RE34 Pullup to V
CC
DIN_ Pullup to V
CC
Table 4. Input Internal Pullup/Pulldown
Resistors
R
L
C
L
DO_+/RIN_+
DO_-/RIN_-
C
L
50Ω
DIN_
GENERATOR
Figure 3. Driver Propagation Delay and Transition Time Test Circuit
V
OS
V
CC
GND
DIN_
R
L
/2
R
L
/2
V
OS
V
OD
DO_-/RIN_-
D0_+/RIN_+
Figure 2. Driver V
OD
and V
OS
Test Circuit
MAX9157
Quad Bus LVDS Transceiver
______________________________________________________________________________________ 11
0
V
OH
V
OL
DIN_
RIN_-
RIN_+
V
OD
V
CC
t
PHLD
50%
0
t
THL
20%
0
80%
80%
0
t
TLH
20%
0 DIFFERENTIAL
t
PLHD
50%
V
OD
= (V
DO_+/RIN_+
- V
DO
_
-/RIN
_
-
)
Figure 4. Driver Propagation Delay and Transition Time
Waveforms
GND
DIN_
DO_-/RIN_-
DO_+/RIN_+
1/4 MAX9157
GENERATOR
+1.2V
50Ω
C
L
R
L
/2
R
L
/2
V
CC
C
L
DE_
Figure 5. Driver High-Impedance Delay Test Circuit
50%
DE_
DO_+/RIN_+ WHEN DIN_ = 0
DO_-/RIN_- WHEN DIN_ = V
CC
D0_+/RIN_+ WHEN DIN_ = V
CC
DO_-/RIN_- WHEN DIN_ = 0
50%
t
PLZ
t
PHZ
t
PZL
t
PZH
V
CC
0
1.2V
V
OL
V
OH
1.2V
50%50%
50%50%
Figure 6. Driver High-Impedance Delay Waveform
DO_+/RIN_+
DO_-/RIN_-
RO_
RECEIVER ENABLED
1/4 MAX9157
*50Ω REQUIRED FOR PULSE GENERATOR TERMINATION.
PULSE
GENERATOR
50Ω*50Ω*
C
L
Figure 7. Receiver Transition Time and Propagation Delay Test Circuit
MAX9157
Quad Bus LVDS Transceiver
12 ______________________________________________________________________________________
DO_-/RIN_-
DO_+/RIN_+
RO_
50%
V
ID
V
OL
V
OH
20%20%
80% 80%
t
PHLD
t
PLHD
t
THL
t
TLH
V
CM
V
CM
50%
Figure 8. Receiver Transition Time and Propagation Delay Timing Diagram
RO_
1/4 MAX9157
C
L
INCLUDES LOAD AND TEST JIG CAPACITANCE.
S
1
= V
CC
FOR t
PZL
AND t
PLZ
MEASUREMENTS.
S
1
= GND FOR t
PZH
AND t
PHZ
MEASUREMENTS.
GENERATOR
50Ω
C
L
R
L
S
1
V
CC
DO_+/RIN_+
DO_-/RIN_-
RE_
Figure 9. Receiver High-Impedance Delay Test Circuit
RE_
RO_ WHEN
V
ID
= -100mV
RO_ WHEN
V
ID
= +100mV
50%
0.5V
0.5V
t
PLZ
t
PHZ
t
PZL
t
PZH
50%
V
CC
V
CC
V
OL
V
OH
GND
0
50%
50%
Figure 10. Receiver High-Impedance Waveforms
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

MAX9157EHJ+

Mfr. #:
Buy MAX9157EHJ+
Manufacturer:
Maxim Integrated
Description:
LVDS Interface IC Quad Bus LVDS Transceiver
Lifecycle:
New from this manufacturer.
Delivery:
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