6
FN8251.1
May 24, 2006
PIN CONFIGURATION
V3MON
V
SS
V
CC
SDA
SCL
3
2
4
1
12
13
11
14
LOWLINE
NC
RESET
7
6
5
8
9
10
V2MON
MR
WP
3
2
4
1
12
13
11
14
7
6
5
8
9
10
V3FAIL
WDO
V2FAIL
V3MON
V
CC
SDA
SCL
WP
V3FAIL
WDO
V
SS
LOWLINE
NC
RESET
V2MON
MR
V2FAIL
X40430, X40434
X40431, X40435
14 Ld SOIC, TSSOP
14 Ld SOIC, TSSOP
PIN DESCRIPTION
Pin Name Function
1V2FAILV2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V
TRIP2
and goes
HIGH when V2MON exceeds V
TRIP2
. There is no power-up reset delay circuitry on this pin.
2V2MONV2 Voltage Monitor Input. When the V2MON input is less than the V
TRIP2
voltage, V2FAIL goes LOW.
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
second power supply with no external components. Connect V2MON to V
SS
or V
CC
when not used. The
V2MON comparator is supplied by V2MON (X40430, X40431) or by the V
CC
input (X40434, X40435).
3LOWLINE
Early Low V
CC
Detect. This CMOS output signal goes LOW when V
CC
< V
TRIP1
and goes high when
V
CC
> V
TRIP1
.
4NCNo connect.
5MR
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re-
main HIGH/LOW until the pin is released and for the t
PURST
thereafter.
6 RESET
/
RESET
RESET Output. (X40431, X40435) This open drain pin is an active LOW output which goes LOW when-
ever V
CC
falls below V
TRIP1
voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t
PURST
) on power-up. It will also stay active until manual reset is released and for
t
PURST
thereafter.
RESET Output. (X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH when-
ever V
CC
falls below V
TRIP1
voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t
PURST
) on power-up. It will also stay active until manual reset is released and for
t
PURST
thereafter.
7V
SS
Ground
8SDASerial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a
pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and
followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the
watchdog time out period results in WDO
going active.
9SCLSerial Clock. The Serial Clock controls the serial bus timing for data input and output.
10 WP Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has
an internal pull down resistor (>10M typical).
11 V3MON V3 Voltage Monitor Input. When the V3MON input is less than the V
TRIP3
voltage, V3FAIL goes LOW.
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
third power supply with no external components. Connect V3MON to V
SS
or V
CC
when not used. The
V3MON comparator is supplied by the V3MON input.
12 V3FAIL
V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than V
TRIP3
and goes
HIGH when V3MON exceeds V
TRIP3
. There is no power-up reset delay circuitry on this pin.
13 WDO
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
14 V
CC
Supply Voltage
X40430, X40431, X40434, X40435
