X40430V14I-A Datasheet X40430S14-A, X40430S14I-A, X40430S14I-B | P13-P15

FN8251.1

May 24, 2006

Serial Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfer. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data. See Figure 9.

The device will respond with an acknowledge after

recognition of a start condition and if the correct

Device Identifier and Select bits are contained in the

Slave Address Byte. If a write operation is selected,

the device will respond with an acknowledge after the

receipt of each subsequent eight bit word. The device

will acknowledge all incoming data and address bytes,

except for the Slave Address Byte when the Device

Identifier and/or Select bits are incorrect.

In the read mode, the device will transmit eight bits of

data, release the SDA line, then monitor the line for an

acknowledge. If an acknowledge is detected and no

stop condition is generated by the master, the device

will continue to transmit data. The device will terminate

further data transmissions if an acknowledge is not

detected. The master must then issue a stop condition

to return the device to Standby mode and place the

device into a known state.

Serial Write Operations

Byte Write

For a write operation, the device requires the Slave

Address Byte and a Word Address Byte. This gives

the master access to any one of the words in the array.

After receipt of the Word Address Byte, the device

responds with an acknowledge, and awaits the next

eight bits of data. After receiving the 8 bits of the Data

Byte, the device again responds with an acknowledge.

The master then terminates the transfer by generating

a stop condition, at which time the device begins the

internal write cycle to the nonvolatile memory. During

this internal write cycle, the device inputs are disabled, so

the device will not respond to any requests from the mas-

ter. The SDA output is at high impedance. See Figure 10.

A write to a protected block of memory will suppress

the acknowledge bit.

Figure 9. Acknowledge Response From Receiver

Figure 10. Byte Write Sequence

Page Write

The device is capable of a page write operation. It is

initiated in the same manner as the byte write opera-

tion; but instead of terminating the write cycle after the

first data byte is transferred, the master can transmit

Data Output from

Transmitter

Data Output

from Receiver

81 9

Start Acknowledge

SCL from

Master

Slave

Address

Byte

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

X40430, X40431, X40434, X40435

FN8251.1

May 24, 2006

an unlimited number of 8-bit bytes. After the receipt of

each byte, the device will respond with an acknowl-

edge, and the address is internally incremented by

one. The page address remains constant. When the

counter reaches the end of the page, it “rolls over” and

goes back to ‘0’ on the same page.

This means that the master can write 16 bytes to the

page starting at any location on that page. If the mas-

ter begins writing at location 10, and loads 12 bytes,

then the first 6 bytes are written to locations 10

through 15, and the last 6 bytes are written to locations

0 through 5. Afterwards, the address counter would

point to location 6 of the page that was just written. If

the master supplies more than 16 bytes of data, then

new data overwrites the previous data, one byte at a

time.

The master terminates the Data Byte loading by issuing

a stop condition, which causes the device to begin the

nonvolatile write cycle. As with the byte write operation,

all inputs are disabled until completion of the internal

write cycle. See Figure 11 for the address, acknowl-

edge, and data transfer sequence.

Stops and Write Modes

Stop conditions that terminate write operations must

be sent by the master after sending at least 1 full data

byte plus the subsequent ACK signal. If a stop is

issued in the middle of a data byte, or before 1 full data

byte plus its associated ACK is sent, then the device

will reset itself without performing the write. The con-

tents of the array will not be effected.

Acknowledge Polling

The disabling of the inputs during high voltage cycles

can be used to take advantage of the typical 5ms write

cycle time. Once the stop condition is issued to indi-

cate the end of the master’s byte load operation, the

device initiates the internal high voltage cycle.

Acknowledge polling can be initiated immediately. To

do this, the master issues a start condition followed by

the Slave Address Byte for a write or read operation. If

the device is still busy with the high voltage cycle then

no ACK will be returned. If the device has completed

the write operation, an ACK will be returned and the

host can then proceed with the read or write operation.

See Figure 13.

Serial Read Operations

Read operations are initiated in the same manner as

write operations with the exception that the R/W

bit of

the Slave Address Byte is set to one. There are three

basic read operations: Current Address Reads, Ran-

dom Reads, and Sequential Reads.

Figure 11. Page Write Operation

Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.

Slave

Address

Byte

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(1)

(1  n  16)

1010 00

address

5 Bytes

n-1

7 Bytes

address

= 6

address pointer

ends here

Addr = 7

X40430, X40431, X40434, X40435

FN8251.1

May 24, 2006

Current Address Read

Internally the device contains an address counter that

maintains the address of the last word read incre-

mented by one. Therefore, if the last read was to

address n, the next read operation would access data

from address n+1. On power-up, the address of the

address counter is undefined, requiring a read or write

operation for initialization.

Upon receipt of the Slave Address Byte with the R/W

bit set to one, the device issues an acknowledge and

then transmits the eight bits of the Data Byte. The

master terminates the read operation when it does not

respond with an acknowledge during the ninth clock

and then issues a stop condition. See figure 15 for the

address, acknowledge, and data transfer sequence.

Figure 13. Acknowledge Polling Sequence

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read

operation, the master must either issue a stop condi-

tion during the ninth cycle or hold SDA HIGH during

the ninth clock cycle and then issue a stop condition.

Random Read

Random read operation allows the master to access any

memory location in the array. Prior to issuing the Slave

Address Byte with the R/W

bit set to one, the master

must first perform a “dummy” write operation. The master

issues the start condition and the Slave Address Byte,

receives an acknowledge, then issues the Word Address

Bytes. After acknowledging receipts of the Word Address

Bytes, the master immediately issues another start con-

dition and the Slave Address Byte with the R/W

bit set to

one. This is followed by an acknowledge from the device

and then by the eight bit word. The master terminates the

read operation by not responding with an acknowledge

and then issuing a stop condition. See Figure 16 for the

address, acknowledge, and data transfer sequence.

A similar operation called “Set Current Address” where

the device will perform this operation if a stop is issued

instead of the second start is shown in Figure 15. The

device will go into standby mode after the stop and all

bus activity will be ignored until a start is detected.

This operation loads the new address into the address

counter. The next Current Address Read operation will

read from the newly loaded address. This operation

could be useful if the master knows the next address it

needs to read, but is not ready for the data.

Sequential Read

Sequential reads can be initiated as either a current

address read or random address read. The first Data

Byte is transmitted as with the other modes; however,

the master now responds with an acknowledge, indicat-

ing it requires additional data. The device continues to

output data for each acknowledge received. The master

terminates the read operation by not responding with an

acknowledge and then issuing a stop condition.

The data output is sequential, with the data from

address n followed by the data from address n + 1. The

address counter for read operations increments through

all page and column addresses, allowing the entire

memory contents to be serially read during one opera-

tion. At the end of the address space the counter “rolls

over” to address 0000h and the device continues to out-

put data for each acknowledge received. See Figure 17

for the acknowledge and data transfer sequence.

ACK

Returned?

Issue Slave Address

Byte (Read or Write)

Byte Load Completed

by Issuing STOP.

Enter ACK Polling

Issue STOP

Issue START

YES

High Voltage Cycle

Complete. Continue

Command Sequence?

Issue STOP

Continue Normal

Read or Write

Command Sequence

PROCEED

YES

X40430, X40431, X40434, X40435

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

X40430V14I-A

Mfr. #:

Buy X40430V14I-A

Manufacturer:

Renesas / Intersil

Description:

IC VOLT MON TRPL EEPROM 14-TSSOP

Lifecycle:

New from this manufacturer.

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X40430V14I-A

X40430V14I-A

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