5
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT2305A
3.3V ZERO DELAY CLOCK BUFFER
SWITCHING CHARACTERISTICS (2305A-1) - INDUSTRIAL
(1,2)
Symbol Parameter Conditions Min. Typ. Max. Unit
t
1 Output Frequency 10pF Load 10 — 133 M Hz
30pF Load 10 — 100
Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 %
t3 Rise Time Measured between 0.8V and 2V — — 2.5 ns
t4 Fall Time Measured between 0.8V and 2V — — 2.5 ns
t5 Output to Output Skew All outputs equally loaded — — 250 ps
t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps
t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 700 ps
tJ Cycle-to-Cycle Jitter, pk - pk Measured at 54-81MHz, loaded outputs — — 170 ps
Other frequencies, loaded outputs 200 ps
t
LOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms
NOTES:
1. REF Input has a threshold voltage of V
DD/2.
2. All parameters specified with loaded outputs.
SWITCHING CHARACTERISTICS (2305A-1H) - INDUSTRIAL
(1,2)
Symbol Parameter Conditions Min. Typ. Max. Unit
t
1 Output Frequency 10pF Load 10 — 133 M Hz
30pF Load 10 — 100
Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 %
Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT <50MHz 45 50 55 %
t3 Rise Time Measured between 0.8V and 2V — — 1.5 ns
t4 Fall Time Measured between 0.8V and 2V — — 1.5 ns
t5 Output to Output Skew All outputs equally loaded — — 250 ps
t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps
t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 700 ps
t8 Output Slew Rate Measured between 0.8V and 2V using Test Circuit #2 1 — — V/ns
tJ Cycle-to-Cycle Jitter, pk - pk Measured at 54-81MHz, loaded outputs — — 170 ps
Other frequencies, loaded outputs 200 ps
tLOCK PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
ZERO DELAY AND SKEW CONTROL
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative
loading can affect and adjust the input/output delay.
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive
load equal to that on the other outputs in order to obtain true zero I/O Delay. If I/O Delay adjustments are needed, use the Output Load Difference diagram
to calculate loading differences between the CLKOUT pin and other outputs. For zero output-to-output skew, all outputs must be loaded equally.
