LT3845A
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BG: The BG pin is the gate drive for the bottom N-channel
MOSFET. Since very fast high currents are driven from
this pin, connect it to the gate of the power MOSFET
with a short and wide, typically 0.02" width, PCB trace to
minimize inductance.
BOOST: The BOOST pin is the supply for the bootstrapped
gate drive and is externally connected to a low ESR ceramic
boost capacitor referenced to SW pin. The recommended
value of the BOOST capacitor, C
BOOST
, is at least 50 times
greater than the total gate capacitance of the topside MOSFET.
In most applications 0.1µF is adequate. The maximum voltage
that this pin sees is V
IN
+ V
CC
, ground referred.
BURST_EN: Burst Mode Operation Enable Pin. This pin also
controls reverse-current inhibit mode of operation. When
the pin voltage is below 0.5V, Burst Mode operation and
reverse-current inhibit functions are enabled. When the pin
voltage is above 0.5V, Burst Mode operation is disabled,
but reverse-current inhibit operation is maintained. In
this mode of operation (BURST_EN = V
FB
) there is a 1mA
minimum load requirement. Reverse-current inhibit is
disabled when the pin voltage is above 2.5V. This pin is
typically shorted to ground to enable Burst Mode operation
and reverse-current inhibit, shorted to V
FB
to disable Burst
Mode operation while enabling reverse-current inhibit,
and connected to V
CC
pin to disable both functions. See
Applications Information section.
C
SS
: The soft-start pin is used to program the supply soft-
start function. Use the following formula to calculate C
SS
for a given output voltage slew rate:
C
SS
= 2µA(t
SS
/1.231V)
The pin should be left unconnected when not using the
soft-start function.
f
SET
: The f
SET
pin programs the oscillator frequency with an
external resistor, R
SET
. The resistor is required even when
supplying external sync clock signal. See the Applications
Information section for resistor value selection details.
PGND: The PGND pin is the high-current ground reference
for internal low side switch driver and the V
CC
regulator
circuit. Connect the pin directly to the negative terminal
of the V
CC
decoupling capacitor. See the Application
Information section for helpful hints on PCB layout of
grounds.
SENSE
: The SENSE
pin is the negative input for the
current sense amplifier and is connected to the V
OUT
side
of the sense resistor for step-down applications.
SENSE
+
: The SENSE
+
pin is the positive input for the current
sense amplifier and is connected to the inductor side of
the sense resistor for step-down applications.
SGND: The SGND pin is the low noise ground reference.
It should be connected to the –V
OUT
side of the output
capacitors. Careful layout of the PCB is necessary to keep
high currents away from this SGND connection. See the
Application Information section for helpful hints on PCB
layout of grounds.
SHDN: The SHDN pin has a precision IC enable threshold
of 1.35V (rising) with 120mV of hysteresis. It is used to
implement an undervoltage lockout (UVLO) circuit. See
Application Information section for implementing a UVLO
function. When the SHDN pin is pulled below a transistor
V
BE
(0.7V), a low current shutdown mode is entered, all
internal circuitry is disabled and the V
IN
supply current
is reduced to approximately 9µA. Typical pin input bias
current is <10nA and the pin is internally clamped to 6V.
If the function is not used, this pin may be tied to V
IN
through a high value resistor.
SW: Reference for V
BOOST
Supply and High Current Return
for Bootstrapped Switch.
SYNC: The Sync pin provides an external clock input for
synchronization of the internal oscillator. R
SET
is set such
that the internal oscillator frequency is 10% to 25% below
the external clock frequency. If unused the Sync pin is
connected to SGND. For more information see “Oscillator
Sync” in the Application Information section of this data
sheet. Sync pin not available in PDIP package.
PIN FUNCTIONS
LT3845A
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TG: The TG pin is the bootstrapped gate drive for the top
N-Channel MOSFET. Since very fast high currents are driven
from this pin, connect it to the gate of the power MOSFET
with a short and wide, typically 0.02” width, PCB trace to
minimize inductance.
V
C
: The V
C
pin is the output of the error amplifier whose
voltage corresponds to the maximum (peak) switch
current per oscillator cycle. The error amplifier is typically
configured as an integrator by connecting an RC network
from the V
C
pin to SGND. This circuit creates the dominant
pole for the converter regulation control loop. Specific
integrator characteristics can be configured to optimize
transient response. When Burst Mode operation is enabled
(see Pin 4 description), an internal low impedance clamp on
the V
C
pin is set at 100mV below the burst threshold, which
limits the negative excursion of the pin voltage. Therefore,
this pin cannot be pulled low with a low impedance source.
If the V
C
pin must be externally manipulated, do so through
a 1kΩ series resistance.
V
CC
: The V
CC
pin is the internal bias supply decoupling
node. Use a low ESR, 1µF or greater ceramic capacitor to
decouple this node to PGND. Most internal IC functions are
PIN FUNCTIONS
powered from this bias supply. An external diode connected
from V
CC
to the BOOST pin charges the bootstrapped
capacitor during the off-time of the main power switch.
Back driving the V
CC
pin from an external DC voltage
source, such as the V
OUT
output of the regulator supply,
increases overall efficiency and reduces power dissipation
in the IC. In shutdown mode this pin sinks 20µA until the
pin voltage is discharged to 0V.
V
FB
: The output voltage feedback pin, V
FB
, is externally
connected to the supply output voltage via a resistive divider.
The V
FB
pin is internally connected to the inverting input
of the error amplifier. In regulation, V
FB
is 1.231V.
V
IN
: The V
IN
pin is the main supply pin and should be
decoupled to SGND with a low ESR capacitor (at least
0.1µF) located close to the pin.
Exposed Pad (SGND) (TSSOP Only): The exposed
leadframe is internally connected to the SGND pin. Solder
the exposed pad to the PCB ground for electrical contact
and optimal thermal performance.
LT3845A
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BLOCK DIAGRAM
+
+
+
+
+
V
IN
UVLO
(<4V)
BST
UVLO
8V
REG
FEEDBACK
REFERENCE
+
1.231V
3.8V
REG
INTERNAL
SUPPLY
RAIL
V
IN
V
CC
UVLO
(<6V)
SHDN
V
REF
DRIVE
CONTROL
NOL
SWITCH
LOGIC
DRIVE
CONTROL
BURST_EN
R
B
V
C
C
SS
SENSE
V
FB
+
V
REF
+ 100mV
FAULT CONDITIONS:
V
IN
UVLO
V
CC
UVLO
V
SHDN
UVLO
2µA
1V
0.5V100mV
ERROR
AMP
Burst Mode
OPERATION
SOFT-START
BURST DISABLE
C
SS
CLAMPED TO
V
REF
+ V
BE
R
SQ
OSCILLATOR
SLOPE COMP
GENERATOR
BOOST
C
BOOST
M1
TG
DRIVER
DRIVER
SW
V
CC
BG
PGND
SYNC
f
SET
R
SET
SENSE
+
3845A FD
BOOSTED
SWITCH
DRIVER
CURRENT
SENSE
COMPARATOR
g
m
+
+
R
S
Q
+
110mV
REVERSE
CURRENT
INHIBIT
10mV
+
SGND
M2
C
OUT
V
OUT
R
SENSE
D2
(OPTIONAL)
L1
D1
C
VCC
C
IN
V
IN
R
C
C
C1
R2
R1
R
A
C
SS
C
C2

LT3845AEFE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators High Voltage Synchronous Current Mode Step-Down Controller with Adjustable Operating Frequency
Lifecycle:
New from this manufacturer.
Delivery:
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