LTC3783
19
3783fb
OPERATION
And so the inductor value is:
L =
IN(MIN)
∆I
L
• f
• D
MAX
=
12V
0.6A • 1MHz
• 0.53 = 11µH
4. R
SENSE
should be:
R
SENSE
=
SENSE(MAX)
I
IN(PEAK)
=
0.5 • 150mV
1.8A
= 42mΩ
5. The diode for this design must handle a maximum DC
output current of 0.7A and be rated for a minimum reverse
voltage of V
OUT
, or 25V. A 1A, 40V diode from Zetex was
chosen for its specifications, especially low leakage at
higher temperatures, which is important for maintaining
dimming range.
6. Voltage and value permitting, the output capacitor usu-
ally consists of some combination of low ESR ceramics.
Based on a maximum output ripple voltage of 1%, or
250mV, the bulk C needs to be greater than:
C
OUT
>
OUT(MAX)
0.01• V
OUT
• f
=
0.7A
0.01• 25V • 1MHz
= 3µF
The RMS ripple current rating for this capacitor needs
to exceed:
I
RMS(COUT)
= I
OUT(MAX)
•
V
OUT
– V
IN(MIN)
V
IN(MIN)
= 0.7A •
25V – 12V
12V
= 0.7A
Based on value and ripple current, and taking physical
size into account, a surface mount ceramic capacitor is a
good choice. A 4.7µF TDK C5750X7R1H475M will satisfy
all requirements in a compact package.
7. The soft-start capacitor should be:
C
SS(MIN)
>
2 • dimming ratio • 50µA • C
OUT
• V
OUT
• R
DS(ON)/SENSE
150mV • 1.2V
>
2 • 3000 • 50µA • 4.7µF • 25V • 42mΩ
= 8µF
8. The choice of an input capacitor for a boost converter
depends on the impedance of the source supply and the
amount of input ripple the converter will safely tolerate.
For this particular design and lab setup, 20µF was found
to be satisfactory.
PC Board Layout Checklist
1. In order to minimize switching noise and improve out-
put load regulation, the GND pad of the LTC3783 should
be connected directly to 1) the negative terminal of the
INTV
CC
decoupling capacitor, 2) the negative terminal of
the output decoupling capacitors, 3) the bottom terminals
of the sense resistors or the source of the power MOSFET,
4) the negative terminal of the input capacitor, and 5) at
least one via to the ground plane immediately under the
exposed pad. The ground trace on the top layer of the PC
board should be as wide and short as possible to minimize
series resistance and inductance.
2. Beware of ground loops in multiple layer PC boards. Try
to maintain one central ground node on the board and use
the input capacitor to avoid excess input ripple for high
output current power supplies. If the ground plane is to
be used for high DC currents, choose a path away from
the small-signal components.
3. Place the C
VCC
capacitor immediately adjacent to the
INTV
CC
and GND pins on the IC package. This capacitor
carries high di/dt MOSFET gate-drive currents. A low ESR
and ESL 4.7µF ceramic capacitor works well here.
4. The high di/dt loop from the bottom terminal of the output
capacitor, through the power MOSFET, through the boost
diode and back through the output capacitors should be
kept as tight as possible to reduce inductive ringing. Excess
inductance can cause increased stress on the power MOSFET
and increase HF noise on the output. If low ESR ceramic
capacitors are used on the output to reduce output noise,
place these capacitors close to the boost diode in order to
keep the series inductance to a minimum.
