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533CB000241DG

P1-P3P4-P6P7-P9P10-P12
Rev. 1.4 6/18 Copyright © 2018 by Silicon Laboratories Si533
Si533
DUAL FREQUENCY CRYSTAL OSCILLATOR (XO)
(10 MH
Z TO 1.4 GHZ)
Features
Applications
Description
The Si533 dual frequency XO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a low jitter clock at high frequencies. The Si533
is available with any-frequency output frequency from 10 to 945 MHz and
select frequencies to 1400 MHz. Unlike a traditional XO, where a different
crystal is required for each output frequency, the Si533 uses one fixed crystal
to provide a wide range of output frequencies. This IC based approach allows
the crystal resonator to provide exceptional frequency stability and reliability.
In addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low jitter clocks in noisy environments
typically found in communication systems. The Si533 IC based XO is factory
configurable for a wide variety of user specifications including frequency,
supply voltage, output format, and temperature stability. Specific
configurations are factory programmed at time of shipment, thereby
eliminating long lead times associated with custom oscillators.
Functional Block Diagram
Available with any-frequency output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
2 selectable output frequencies
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Pin 1 output enable (OE)
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
SONET/SDH
Networking
SD/HD video
Clock and data recovery
FPGA/ASIC clock generation
Any-frequency
10–1400 MHz
DSPLL®
Clock
Synthesis
V
DD
CLK+CLK–
OE
GND
FS
Fixed
Frequency
XO
Ordering Information:
See page 7.
Pin Assignments:
See page 6.
(Top View)
Si5602
1
2
3
6
5
4GND
FS
V
DD
CLK+
CLK–
OE
1
2
3
6
5
4GND
FS
V
DD
CLK+
NC
OE
LVDS/LVPECL/CML
CMOS
REVISION D
Si533
2 Rev. 1.4
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Units
Supply Voltage
1
V
DD
3.3 V option 2.97 3.3 3.63 V
2.5 V option 2.25 2.5 2.75 V
1.8 V option 1.71 1.8 1.89 V
Supply Current I
DD
Output enabled
LVPECL
CML
LVDS
CMOS
—
—
—
—
111
99
90
81
121
108
98
88
mA
Tristate mode — 60 75 mA
Output Enable (OE)
and Frequency Select (FS)
2
V
IH
0.75 x V
DD
——V
V
IL
——0.5V
Operating Temperature Range T
A
–40 — 85 ºC
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2. OE and FS pins include a 17 k pullup resistor to V
DD
.
Table 2. CLK± Output Frequency Characteristics
Parameter Symbol Test Condition Min Typ Max Units
Nominal Frequency
1,2
f
O
LVPECL/LVDS/CML
10 — 945
MHz
CMOS
10 — 160
MHz
Initial Accuracy
f
i
Measured at +25 °C at time of
shipping
— ±1.5 — ppm
Temperature Stability
1,3
–7
–20
–50
—
—
—
+7
+20
+50
ppm
Aging f
a
Frequency drift over first year — — ±3 ppm
Frequency drift over 20 year life — — ±10 ppm
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to f
O
.
Si533
Rev. 1.4 3
Total Stability
Temp stability = ±7 ppm — — ±20 ppm
Temp stability = ±20 ppm — — ±31.5 ppm
Temp stability = ±50 ppm — — ±61.5 ppm
Powerup Time
4
t
OSC
——10ms
Settling Time After FS Change t
FRQ
——10ms
Table 3. CLK± Output Levels and Symmetry
Parameter Symbol Test Condition Min Typ Max Units
LVPECL Output Option
1
V
O
mid-level V
DD
– 1.42 — V
DD
– 1.25 V
V
OD
swing (diff) 1.1
—
1.9 V
PP
V
SE
swing (single-ended) 0.55
—
0.95 V
PP
LVDS Output Option
2
V
O
mid-level
1.125 1.20 1.275 V
V
OD
swing (diff)
0.5 0.7 0.9 V
PP
CML Output Option
2
V
O
2.5/3.3 V option mid-level — V
DD
– 1.30 — V
1.8 V option mid-level — V
DD
– 0.36 — V
V
OD
2.5/3.3 V option swing (diff) 1.10 1.50 1.90 V
PP
1.8 V option swing (diff) 0.35 0.425 0.50 V
PP
CMOS Output Option
3
V
OH
I
OH
=32mA
0.8 x V
DD
—
V
DD
V
V
OL
I
OL
=32mA — — 0.4 V
Rise/Fall time (20/80%)
t
R,
t
F
LVPECL/LVDS/CML — — 350 ps
CMOS with C
L
=15pF — 1 — ns
Symmetry (duty cycle)
SYM LVPECL: V
DD
– 1.3 V (diff)
LVDS: 1.25 V (diff)
CMOS: V
DD
/2
45 — 55 %
Notes:
1. 50 to V
DD
– 2.0 V.
2. R
term
= 100 (differential).
3. C
L
= 15 pF
Table 2. CLK± Output Frequency Characteristics (Continued)
Parameter Symbol Test Condition Min Typ Max Units
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to f
O
.
P1-P3P4-P6P7-P9P10-P12

533CB000241DG

Mfr. #:
Buy 533CB000241DG
Manufacturer:
Silicon Labs
Description:
Standard Clock Oscillators Differential/single-ended; dual frequency XO; OE pin 1; 10-1417 MHz
Lifecycle:
New from this manufacturer.
Delivery:
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