17
FN6436.0
June 18, 2007
detection scheme – especially during start-up. The user is
directed to the layout guidelines and component selection
sections to avoid problems during initial evaluation and
prototype PCB generation.
V
ON
-Slice Circuit
The V
ON
-slice Circuit functions as a three way multiplexer,
switching the voltage on COM between ground, DRN and
SRC, under control of the start-up sequence and the CTL pin.
Once the start-up sequence has completed, CTL is enabled
and acts as a multiplexer control such that if CTL is low,
COM connects to DRN through a 5internal MOSFET, and
if CTL is high, COM connects to SRC via a 30MOSFET.
The slew rate of start-up of the switch control circuit is mainly
restricted by the load capacitance at COM pin, as in
Equation 16:
Where V
g
is the supply voltage applied to the switch control
circuit, R
i
is the resistance between COM and DRN or SRC
including the internal MOSFET r
DS(ON)
, the trace resistance
and the resistor inserted; R
L
is the load resistance of the
switch control circuit, and C
L
is the load capacitance of the
switch control circuit.
In the “Typical Application Circuit” on page 18, R
8
, R
9
and
C
8
give the bias to DRN based on Equation 17:
and R
10
can be adjusted to adjust the slew rate.
Op Amps
The ISL97642 has 3 amplifiers respectively. The op amps
are typically used to drive the TFT-LCD backplane (V
COM
)
or the gamma-correction divider string. They feature rail-to-
rail input and output capability. They are unity gain stable,
and have low power consumption (typical 600A per
amplifier). The ISL97642 has a -3dB bandwidth of 12MHz
while maintaining a 10V/s slew rate.
Short Circuit Current Limit
The ISL97642 will limit the short circuit current to ±180mA if
the output is directly shorted to the positive or the negative
supply. If an output is shorted for a long time, the junction
temperature will trigger the Over-Temperature Protection
limit and, hence, the part will shut down.
Driving Capacitive Loads
ISL97642 can drive a wide range of capacitive loads. As
load capacitance increases, however, the -3dB bandwidth of
the device will decrease and the peaking will increase. The
amplifiers drive 10pF loads in parallel with 10k with just
1.5dB of peaking, and 100pF with 6.4dB of peaking. If less
peaking is desired in these applications, a small series
resistor (usually between 5 and 50) can be placed in
series with the output. However, this will obviously reduce
the gain. Another method of reducing peaking is to add a
“snubber” circuit at the output. A snubber is a shunt load
consisting of a resistor in series with a capacitor. Values of
150 and 10nF are typical. The advantage of a snubber is
that it does not draw any DC load current and reduce the
gain.
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point, the device will be latched off
until either the input supply voltage or enable is cycled.
Layout Recommendation
The devices performance (including efficiency, output noise,
transient response and control loop stability) is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place VREF and VDD bypass capacitors close to the
pins.
3. Reduce the loop with large AC amplitudes and fast slew
rate.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point.
6. The exposed die plate, on the underneath of the
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers (if available) to
maximize thermal dissipation away from the IC.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
8. A signal ground plane, separate from the power ground
plane and connected to the power ground pins only at the
exposed die plate, should be used for ground return
connections for feedback resistor networks (R
1
, R
11
,
R
41
) and the V
REF
capacitor, C
22
, the C
DELAY
capacitor
C
7
and the integrator capacitor C
23
.
9. Minimize feedback input track lengths to avoid switching
noise pick-up.
A demo board is available to illustrate the proper layout
implementation.
V
t
--------
V
g
R
i
R
L
C
L
------------------------------------
=
(EQ. 16)
V
DRN
V
ON
R
9
A
VDD
R
8
+
R
8
R
9
+
-------------------------------------------------------------
=
(EQ. 17)
ISL97642
