ADN2890 Data Sheet
Rev. B | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic I/O Description
1 AVCC Power Analog Power
2 PIN Input Differential Data Input
3 NIN Input Differential Data Input
4 AVEE Power Analog Ground
5 THRADJ Input LOS Threshold Adjust Resistor
6 CAZ1 Offset Correction Loop Capacitor
7 CAZ2 Offset Correction Loop Capacitor
8 LOS Output LOS Detector Output
9 DRVEE Power Output Buffer Ground
10 OUTN Output Differential Data Output
11 OUTP Output Differential Data Output
12 DRVCC Power Output Buffer Power
13 SQUELCH Input Disable Outputs
14 RSSI_OUT Output Average Current Output
15 PD_VCC Power Power Input for RSSI Measurement
16 PD_CATHODE Output Photodiode Bias Voltage
Exposed Pad Pad Power Connect to Ground
04509-0-004
AVCC
THRADJ
CAZ1
CAZ2
LOS
PIN
NIN
AVEE
DRVCC
NOTES
1.THE EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE MUST BE CONNECTED
TO THE GND PLANE WITH FILLED VIAS.
OUTN
DRVEE
OUTP
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
PD_CATHODE
PD_VCC
RSSI_OUT
SQUELCH
TOP VIEW
(Not To Scale)
ADN2890
Data Sheet ADN2890
Rev. B | Page 7 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. RSSI Output vs. Average PIN Photodiode Current
Figure 4. L
OS
Trip Point vs. Threshold Adjust Resistor
Figure 5. Typical PSRR vs. Supply-Noise Frequency
Figure 6. Eye Diagram at 3.2 Gb/s
Figure 7. Eye Diagram at 2.488 Gb/s
04509-0-002
0
0 0.1 0.2 0.3 0.4 0.5
RSSI_IN (mA)
0.6 0.7 0.8 0.9 1.0
RSSI_OUT (mA)
0.88
0.96
0.80
0.72
0.64
0.56
0.48
0.40
0.32
0.24
0.16
0.08
04509-0-009
0
0.002
0.004
0.006
0.008
0.010
0.012
10 100 1k 10k
R
TH
(
)
100k
L
OS
TRIP POINT (V)
0.014
04509-0-010
0
10
20
30
40
50
60
100k 1M
SUPPLY-NOISE FREQUENCY (Hz)
10M
SUPPLY-NOISE REJECTION (dB)
70
04509-0-020
VERTICAL SCALE: 100mV/DIV
04509-0-021
VERTICAL SCALE: 100mV/DIV
ADN2890 Data Sheet
Rev. B | Page 8 of 12
THEORY OF OPERATION
LIMAMP
Input Buffer
The limiting amplifier has differential inputs (PIN/NIN), with
an internal 50 Ω termination. The ROSA (receive optical sub-
assembly) is typically ac-coupled to the ADN2890 inputs,
although dc coupling is possible.
An internal offset correction loop requires that a capacitor be
connected between the CAZ1 and CAZ2 pins. A 0.01 µF
capacitor provides a low frequency cutoff of 2 kHz.
CML Output Buffer
The ADN2890 provides CML outputs, OUTP/OUTN. The
outputs are internally terminated with 50 Ω to VCC.
The outputs can be kept at a static voltage by driving the
SQUELCH pin to a logic high. The SQUELCH pin can be
driven directly by the LOS pin, which automatically disables
the LIMAMP outputs in situations with no data input.
LOSS OF SIGNAL (LOS) DETECTOR
The receiver front-end LOS detector circuit indicates when the
input signal level has fallen below the user-adjustable threshold.
The threshold is set by a resistor connected between the
THRADJ pin and V
EE
. The ADN2890 LOS circuit has a trip
point down to <3.0 mV with >3 dB electrical hysteresis to
prevent chatter at the LOS output. The LOS output is an open-
collector output that must be pulled up externally with a 4.7 kΩ
to 10 kΩ resistor.
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)
The ADN2890 has an on-chip RSSI circuit that automatically
detects the average received power based on a direct measure-
ment of the PIN photodiodes current. The photodiode bias is
supplied by the ADN2890, which allows a very accurate, on-
chip, average power measurement based on the amount of
current supplied to the photodiode. The output of the RSSI is a
current that is directly proportional to the average amount of
PIN photodiode current. Placing a resistor between the
RSSI_OUT pin and GND converts the current to a GND
referenced voltage. This function eliminates the need for
external RSSI circuitry in SFF-8472 compliant optical receivers.
SQUELCH MODE
Driving the SQUELCH input to a logic high disables the
limiting amplifier outputs. The SQUELCH input can be
connected to the LOS output to keep the limiting amplifier
outputs at a static voltage level anytime the input level to the
limiting amplifier drops below the programmed LOS threshold.

ADN2890ACPZ-RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Limiting Amplifiers 2.7Gbps Limiting Amplifier.I.C.
Lifecycle:
New from this manufacturer.
Delivery:
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