LTC1287
5
1287fa
CCHARA TERIST
ICS
UW
AT
Y
P
I
CA
LPER
F
O
R
C
E
R
SOURCE
– (Ω)
100
0
MAXIMUM CLK FREQUENCY* (MHz)
300
400
500
1k 10k 100k
LTC G10
200
100
V
CC
= 3V
V
REF
= 2.5V
CLK = 500kHz
+IN
–IN
+V
IN
R
SOURCE
–
R
SOURCE
+ (Ω)
100 1k 10k
LTC1287 G13
1
S & H ACQUISITION TIME TO 0.02% (µs)
10
100
+
–
V
IN
R
SOURCE
+
V
REF
= 2.5V
V
CC
= 3V
T
A
= 25°C
0V TO 2.5V INPUT STEP
Sample-and-Hold Acquisition
Time vs Source Resistance
AMBIENT TEMPERATURE (°C)
–50
0
INPUT CHANNEL LEAKAGE CURRENT (nA)
100
300
400
500
1000
700
–10
30
50 130
LTC1287 G14
200
800
900
600
–30 10
70 90
110
ON CHANNEL
OFF CHANNEL
GUARANTEED
Input Channel Leakage Current vs
Temperature
REFERENCE VOLTAGE (V)
0
0
PEAK-TO-PEAK NOISE ERROR (LSB)
0.2
0.3
0.4
0.5
0.6
0.7
0.5
1.0
1.5 2.0
LTC1287 G15
2.5
0.8
0.9
1.0
0.1
3.0
LTC1287 NOISE = 200µV
P-P
Noise Error vs Reference Voltage
Maximum Clock Rate vs Source
Resistance
Minimum Clock Rate for 0.1LSB
Error**
Maximum Filter Resistor vs Cycle
Time
*** MAXIMUM R
FILTER
REPRESENTS THE FILTER RESISTOR VALUE AT WHICH A 0.1LSB
CHANGE IN FULL SCALE ERROR FROM ITS VALUE AT R
FILTER
= 0Ω IS FIRSTDETECTED.
* MAXIMUM CLK FREQUENCY REPRESENTS THE CLK FREQUENCY AT WHICH A 0.1LSB
SHIFT IN THE ERROR AT ANY CODE TRANSITION FROM ITS 500kHz VALUE IS FIRST DETECTED.
** AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY
(∆ERROR ≤ 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY
CODE TRANSITION FROM ITS 500kHz VALUE IS FIRST DETECTED.
PI FU CTIO S
U
UU
CYCLE TIME (µs)
10
MAXIMUM R
FILTER
*** (Ω)
100
1k
10k
10 1000 10000
LTC1287 G12
1
100
+
–
V
IN
C
FILTER
≥1µF
R
FILTER
AMBIENT TEMPERATURE (°C)
–50
MINIMUM CLK FREQUENCY (MHz)
0.05
0.10
0.15
0.20
–25
02550
LTC1287 G11
75 100
0.25
V
CC
= 3V
CS (Pin 1): Chip Select Input. A logic low on this input
enables the LTC1287.
+IN, –IN (Pin 2,3): Analog Inputs. These inputs must be
free of noise with respect to GND.
GND (Pin 4): Analog Ground GND should be tied directly
to an analog ground plane.
V
REF
(Pin 5): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to GND.
D
OUT
(Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the serial
data transfer.
V
CC
(Pin 8): Positive Supply. This supply must be kept free
of noise and ripple by bypassing directly to the analog
ground plane.
