MAX7036
300MHz to 450MHz ASK Receiver
with Internal IF Filter
_______________________________________________________________________________________ 7
Functional Diagram
Pin Description (continued)
PIN NAME FUNCTION
13 DCOC
DC Offset Capacitor Connection. This is for the RSSI amplifier. Connect a 1μF capacitor from this pin
to ground (see the Typical Application Circuit).
14 OPP
Noninverting Op-Amp Input. This is for the Sallen-Key data filter. Connect a capacitor from this pin to
GND. The value of the capacitor is determined by the data-filter bandwidth.
15 DFFB
Data-Filter Feedback Input. Input for the feedback of the Sallen-Key data filter. Connect a capacitor
from this pin to DSP. The value of the capacitor is determined by the data-filter bandwidth.
16 DSP
Positive Data-Slicer Input. Connect a capacitor from this pin to DFFB. The value of the capacitor is
determined by the data-filter bandwidth.
17 DSN Negative Data-Slicer Input
18 PDOUT Peak-Detector Output
19 V
DD
Power-Supply Voltage Input. For 5.0V operation, V
DD
is the input to an on-chip voltage regulator
whose 3.2V output drives AVDD. Bypass to ground with a 0.1μF capacitor as close as possible to the
device (see the Typical Application Circuit).
20 DATAOUT Digital Baseband Data Output
—EP
Exposed Pad. Internally connected to ground. Connect to a large ground plane using multiple vias to
maximize thermal and electrical performance.
MAX7036
EP*
*EXPOSED PAD.
CONNECT TO GND.
3.2V
REGULATOR
PEAK
DETECTOR
REF
REF
AGC
DATAOUT DSN PDOUT DSP OPP DFFB
LNAOUT
MIXIN1
MIXIN2
XTAL1
XTAL2
ENABLE
V
DD
AVDD
DVDD
LNAIN
IFC1 IFC2 IFC3 DCOC
PLL
3
2
1
19
4
12
5
687 10 9 1311
20 17 18 16 14 15
MAX7036
Detailed Description
The MAX7036 CMOS RF receiver, and a few external
components, provide the complete receiver chain from
the antenna to the digital output data. Depending on
signal power and component selection, data rates as
high as 33kbps Manchester (66kbps NRZ) can be
achieved.
The MAX7036 is designed to receive binary ASK/OOK
data modulated in the 300MHz to 450MHz frequency
range. ASK modulation uses a difference in amplitude
of the carrier to represent digital data.
Voltage Regulator
For operation with a single 3.0V to 3.6V supply voltage,
connect AVDD, DVDD, and V
DD
to the supply voltage.
For operation with a single 4.5V to 5.5V supply voltage,
connect V
DD
to the supply voltage. An on-chip voltage
regulator drives the AVDD pin to approximately 3.2V.
For proper operation, connect DVDD and AVDD togeth-
er. Bypass V
DD
and AVDD to GND with 0.1μF capaci-
tors placed as close as possible to the device. Bypass
DVDD to GND with a 0.01μF capacitor (see the
Typical
Application Circuit
).
Low-Noise Amplifier
The LNA is an nMOS cascode amplifier. The LNA and
mixer have a combined 55dB voltage gain. The gain
and noise figures are dependent on both the antenna-
matching network at the LNA input and the LC tank net-
work between the LNA output and the mixer inputs.
L2 and C1 comprise the LC tank filter connected to
LNAOUT (see the
Typical Application Circuit
). L2 also
serves as a bias inductor to LNAOUT. Bypass the
power-supply side of L2 to GND with a capacitor that
provides a low-impedance path at the RF carrier fre-
quency (e.g., 220pF). Select L2 and C1 to resonate at
the desired RF input frequency. The resonant frequen-
cy is given by:
where L
TOTAL
= L2 + L
PARASITICS
and C
TOTAL
= C1 +
C
PARASITICS
.
L
PARASITICS
and C
PARASITICS
include inductance and
capacitance of the PCB traces, package pins, mixer
input impedance, LNA output impedance, etc. At high
frequencies, these parasitics can have a dramatic
effect on the tank filter center frequency and must not
be ignored. The total parasitic capacitance is generally
4pF to 6pF. Adjust L2 and C1 accordingly to achieve
the desired tank center frequency.
Automatic Gain Control (AGC)
The AGC circuit monitors the RSSI output. The AGC
switches to its low-gain state when the RSSI output
reaches 2.2V. The AGC gain reduction is typically
29dB, corresponding to an RSSI voltage drop of
435mV. The LNA resumes high-gain mode when the
RSSI level drops back below 1.67V for 13ms for
315MHz and 10ms for 433MHz operation. The AGC has
a hysteresis of 5dB. With this AGC function, the
MAX7036 can reliably produce an ASK output for RF
input levels up to 0dBm, with modulation depth of
30dB.
Mixer
The mixer cell is a double-balanced mixer that performs
a downconversion of the RF input to a typical IF of
200kHz from either a high-side or a low-side injected LO.
The mixer output drives the input of the on-chip IF filter.
Phase-Locked Loop (PLL)
The PLL block contains a phase detector, charge pump,
integrated loop filter, VCO, asynchronous clock dividers,
and crystal-oscillator driver. Besides the crystal, this PLL
does not require any external components. The VCO
generates the LO. The relationship between the RF, IF,
and crystal reference frequencies is given by:
where f
LO
= f
RF
±f
IF
Received-Signal-Strength Indicator (RSSI)
The RSSI circuit provides a DC output proportional to
the logarithm of the input power level. RSSI output volt-
age has a slope of about 14.5mV/dB (of input
power).The RSSI monotonic dynamic range exceeds
80dB. This includes the 30dB of AGC.
Applications Information
Crystal Oscillator
The crystal (XTAL) oscillator in the MAX7036 is
designed to present a capacitance of approximately
4pF between XTAL1 and XTAL2. In most cases, this
corresponds to a 6pF load capacitance applied to the
external crystal when typical PCB parasitics are added.
The MAX7036 is designed to operate with a typical
10pF load capacitance crystal. It is very important to
use a crystal with a load capacitance equal to the
capacitance of the MAX7036 crystal oscillator plus
PCB parasitics. If a crystal designed to oscillate with a
different load capacitance is used, the crystal is pulled
away from its stated operating frequency, introducing
f
f
XTAL
LO
=
32
f
LC
RF
TOTAL TOTAL
=
×
1
2π
300MHz to 450MHz ASK Receiver
with Internal IF Filter
8 _______________________________________________________________________________________
an error in the reference frequency. A crystal designed
to operate at a higher load capacitance than the value
specified for the oscillator is always pulled higher in fre-
quency. Adding capacitance to increase the load
capacitance on the crystal increases the start-up time
and may prevent oscillation altogether.
In actuality, the oscillator pulls every crystal. The crys-
tal’s natural frequency is really below its specified fre-
quency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
where:
f
p
is the amount the crystal frequency is pulled in
ppm.
C
M
is the motional capacitance of the crystal.
C
CASE
is the case capacitance.
C
SPEC
is the specified load capacitance.
C
LOAD
is the actual load capacitance.
When the crystal is loaded, as specified (i.e., C
LOAD
=
C
SPEC
), the frequency pulling equals zero.
It is possible to use an external reference oscillator in
place of a crystal to drive the VCO. AC-couple the exter-
nal oscillator to XTAL1 with a 1000pF capacitor. Drive
XTAL1 with a signal level of approximately -10dBm. AC-
couple XTAL2 to ground with a 1000pF capacitor.
IF Filter
The IF filter is a 2nd-order Butterworth lowpass filter
preceded by a low-frequency DC block. The lowpass
filter is implemented as a Sallen-Key filter using an
internal op amp and two on-chip 22kΩ resistors. The
pole locations are set by the combination of the on-chip
resistors and two external capacitors (C9 and C10,
Figure 1). The values of these two capacitors for a 3dB
cutoff frequency of 400kHz are given below:
Because the stray shunt capacitance at each of the
pins (IFC1 and IFC2) on a typical PCB is approximately
2pF, choose the value of the external capacitors to be
approximately 2pF lower than the desired total capaci-
tance. Therefore, the practical values for C9 and C10
are 22pF and 10pF, respectively.
Data Filter
The data filter is implemented as a 2nd-order lowpass
Sallen-Key filter. The pole locations are set by the combi-
nation of two on-chip resistors and two external capaci-
tors. Adjusting the value of the external capacitors
changes the corner frequency to optimize for different
data rates. Set the corner frequency to approximately
1.5 times the fastest Manchester expected data rate
from the transmitter. Keeping the corner frequency near
the data rate rejects any noise at higher frequencies,
resulting in an increase in receiver sensitivity.
The configuration shown in Figure 2 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works with the coefficients in Table 1.
where f
C
is the desired corner frequency.
C
a
kf
c
6
4 100
=
()()
()
π
C
b
ak f
c
5
100
=
()()
()
π
C
Rf
k
c
9
1
1 414
1
1 414 22 3 14 4
=
( )()()
()
=
()()()
.
..
π
Ω
000
26
10
1
2 828
1
2 828
kHz
pF
C
Rf
c
()
=
=
( )()()
()
=
(
.
.
π
))( )( )( )
=
22 3 14 400
13
kkHz
pF
Ω .
f
C
CC CC
P
M
CASE LOAD CASE SPEC
=
+
+
×
2
11
10
6
MAX7036
300MHz to 450MHz ASK Receiver
with Internal IF Filter
_______________________________________________________________________________________ 9
MAX7036
C9
22kΩ22kΩ
C10
10
IFC1
9
IFC2
11
IFC3
Figure 1. Sallen-Key Lowpass IF Filter

MAX7036GTP/V+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
RF Receiver 300MHz to 450MHz ASK Receiver with Internal IF Filter
Lifecycle:
New from this manufacturer.
Delivery:
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