AD7237A/AD7247A
REV. 0
–8–
CIRCUIT INFORMATION
D/A Section
The AD7237A/AD7247A contains two 12-bit voltage-mode D/A
converters consisting of highly stable thin film resistors and high
speed NMOS single-pole, double-throw switches. The output
voltage from the converters has the same polarity as the refer-
ence voltage, REF IN, allowing single supply operation. The
simplified circuit diagram for one of the D/A converters is
shown in Figure 2.
The REF IN voltage is internally buffered by a unity gain
amplifier before being applied to the D/A converters. The D/A
converters are configured and scaled for a 5 V reference and the
device is tested with 5 V applied to REF IN.
Figure 2. D/A Simplified Circuit Diagram
Internal Reference
The AD7237A/AD7247A has an on-chip temperature compen-
sated buried Zener reference (see Figure 3) which is factory
trimmed to 5 V ±30 mV (±50 mV for T Version). The reference
voltage is provided at the REF OUT pin. This reference can be
used to provide the reference voltage for the D/A converter (by
connecting the REF OUT pin to the REF IN pin) and the offset
voltage for bipolar outputs (by connecting REF OUT to R
OFS
).
The reference voltage can also be used as a reference for other
components and is capable of providing up to 500 µA to an ex-
ternal load. The maximum recommended capacitance on REF
OUT for normal operation is 50 pF. If the reference is required
for external use, it should be decoupled to AGND (GND) with
a 200 Ω resistor in series with parallel combination of a 10 µF
tantalum capacitor and a 0.1 µF ceramic capacitor.
Figure 3. Internal Reference
External Reference
In some applications, the user may require a system reference or
some other external reference to drive the AD7237A/ AD7247A
reference input. References such as the AD586 5 V reference
provide the ideal external reference source for the AD7237A/
AD7247A (see Figure 9).
Op Amp Section
The output of the voltage-mode D/A converter is buffered by a
noninverting CMOS amplifier. The R
OFS
input allows different
output voltage ranges to be selected. The buffer amplifier is ca-
pable of developing +10 V across a 2 kΩ load to GND. The
output amplifier can be operated from a single +12 V to +15 V
supply by tying V
SS
= 0 V. The amplifier can also be operated
from dual supplies (±12 V to ±15 V) to allow a bipolar output
range of –5 V to +5 V. The advantages of having dual supplies
for the unipolar output ranges are faster settling time to voltages
near 0 V, full sink capability of 2.5 mA maintained over the en-
tire output range and the elimination of the effects of negative
offsets on the transfer characteristic (outlined previously). A
plot of the single supply output sink capability of the amplifier is
shown in the Typical Performance Graphs section.
INTERFACE LOGIC INFORMATION—AD7247A
Table I shows the truth table for AD7247A operation. The part
contains a single, parallel 12-bit latch for each DAC. It can be
treated as two independent DACs, each with its own
CS input
and a common
WR input. CSA and WR control the loading of
data to the DAC A latch while
CSB and WR control the loading
of the DAC B latch. If
CSA and CSB are both low, with WR
low, the same data will be written to both DAC latches. All con-
trol signals are level triggered and therefore either or both
latches can be made transparent. Input data is latched to the re-
spective latch on the rising edge of
WR. Figure 4 shows the in-
put control logic for the AD7247A, while the write cycle timing
diagram for the part is shown in Figure 5.
Figure 4. AD7247A Input Control Logic
Figure 5. AD7247A Write Cycle Timing Diagram
