MAX801L/M/N, MAX808L/M/N
MAX801 Watchdog Timer
The watchdog monitors the µP’s activity. If the µP does
not toggle the watchdog input (WDI) within 1.6sec,
reset asserts for the reset timeout period. The internal
1.6sec timer is cleared when reset asserts or when a
transition (low-to-high or high-to-low) occurs at WDI
while reset is not asserted. The timer remains cleared
and does not count as long as reset is asserted. It
starts counting as soon as reset is released (Figure 5).
Supply current is typically reduced by 10µA when WDI
is at a valid logic level. To disable the watchdog func-
tion, leave WDI unconnected. An internal voltage
divider sets WDI to about mid-supply, disabling the
watchdog timer/counter.
MAX808 Chip-Enable Gating
The MAX808 provides internal gating of chip-enable
(CE) signals to prevent erroneous data from corrupting
CMOS RAM in the event of a power failure. During nor-
mal operation, the CE gate is enabled and passes all
CE transitions. When reset is asserted, this path
becomes disabled, preventing erroneous data from
corrupting the CMOS RAM. The MAX808 uses a series
transmission gate from the chip-enable input (CE IN) to
the chip-enable output (CE OUT) (Figure 1). The 8ns
max chip-enable propagation from CE IN to CE OUT
enables the MAX808 to be used with most µPs.
The MAX808 also features write-cycle-completion cir-
cuitry. If V
CC
falls below the reset threshold while the
µP is writing to RAM, the MAX808 holds the CE gate
enabled for 18µs to allow the µP to complete the write
instruction. If the write cycle has not completed by the
end of the 18µs period, the CE transmission gate turns
off and CE OUT goes high. If the µP completes the
write instruction during the 18µs period, the CE gate
turns off (high impedance) and CE OUT goes high as
soon as the µP pulls CE IN high. CE OUT remains high,
even if CE IN falls low for any reason (Figure 6).
Chip-Enable Input
CE IN is high impedance (disabled mode) while reset is
asserted. During a power-down sequence when V
CC
passes the reset threshold, the CE transmission gate
disables. CE IN becomes high impedance 18µs after
reset asserts, provided CE IN is still low. If the µP com-
pletes the write instruction during the 18µs period, the
CE gate turns off. CE IN becomes high impedance as
soon as the µP pulls CE IN high. CE IN remains high
impedance even if the signal at CE IN falls low (Figure
6). During a power-up sequence, CE IN remains high
impedance (regardless of CE IN activity) until reset is
deasserted following the reset timeout period.
In high-impedance mode, the leakage currents into this
input are ±1µA max over temperature. In low-imped-
ance mode, the impedance of CE IN appears as a 75Ω
resistor in series with the load at CE OUT.
The propagation delay through the CE transmission
gate depends on both the source impedance of the
drive to CE IN and the capacitive loading on CE OUT
(see the Chip-Enable Propagation Delay vs. CE OUT
Load Capacitance graph in the Typical Operating
Characteristics). The CE propagation delay is produc-
tion tested from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ω driver and 50pF of load
capacitance (Figure 7). For minimum propagation
delay, minimize the capacitive load at CE OUT and use
a low-output-impedance driver.
8-Pin µP Supervisory Circuits
with ±1.5% Reset Accuracy
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