Data Sheet AD841
Rev. C | Page 9 of 16
Figure 22. Inverting Amplifier Configuration (PDIP Pinout)
Figure 23. Inverter Large Signal Pulse Response
Figure 24. Inverter Small Signal Pulse Response
Figure 25. Unity-Gain Buffer Amplifier Configuration (PDIP Pinout)
Figure 26. Buffer Large Signal Pulse Response
Figure 27. Buffer Small Signal Pulse Response
11
6
4
5
10
+
AD841
+V
S
–V
S
2.2µF
0.1µF
2.2µF
0.1µF
V
OUT
499Ω
49.9Ω
R
B
499Ω
R
F
1kΩ
R
IN
1kΩ
HP3314A
FUNCTION
GENERATOR
OR
EQUIVALENT
11340-022
100
90
10
0%
2V
50ns
11340-023
100
90
10
0%
50mV 50ns
11340-024
49.9Ω
R
IN
100Ω
HP3314A
FUNCTION
GENERATOR
OR
EQUIVALENT
V
IN
11
6
4
5
10
+
AD841
+V
S
–V
S
2.2µF
0.1µF
2.2µF
0.1µF
V
OUT
499Ω
R
B
120Ω
1
1340-025
100
90
10
0%
2V 50ns
11340-026
100
90
10
0%
50mV 50ns
11340-027
AD841 Data Sheet
Rev. C | Page 10 of 16
THEORY OF OPERATION
OFFSET NULLING
The input offset voltage of the AD841 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 28 can be used.
Figure 28. Offset Nulling (PDIP Pinout)
INPUT CONSIDERATIONS
An input resistor (R
IN
in Figure 25) is recommended in circuits
where the input to the AD841 is subjected to transient or
continuous overload voltages exceeding the ±6 V maximum
differential limit. This resistor provides protection for the input
transistors by limiting the maximum current that can be forced
into the input.
For high performance circuits it is recommended that a resistor
(R
B
in Figure 22 and Figure 25) be used to reduce bias current
errors by matching the impedance at each input. The output
voltage error caused by the offset current is more than an order
of magnitude less than the error present if the bias current error
is not removed.
AD841 SETTLING TIME
Figure 29 and Figure 31 show the settling performance of the
AD841 in the test circuit shown in Figure 30.
Settling time is defined as the interval of time from the
application of an ideal step function input until the closed-loop
amplifier output has entered and remains within a specified
error band.
This definition encompasses the major components, which
comprise settling time. They include
Propagation delay through the amplifier
Slewing time to approach the final output value
The time of recovery from the overload associated
with slewing
Linear settling to within the specified error band
Expressed in these terms, the measurement of settling time
is obviously a challenge and needs to be done accurately to
assure the user that the amplifier is worth consideration for
the application.
Figure 29. AD841 0.01% Settling Time
Figure 30. Settling Time Test Circuit
Measurement of the 0.01% settling in 110 ns was accomplished
by amplifying the error signal from a false summing junction
with a very high speed proprietary hybrid error amplifier
specially designed to enable testing of small settling errors.
The device under test was driving a 500 Ω load. The input to
the error amp is clamped to avoid possible problems associated
with the overdrive recovery of the oscilloscope input amplifier.
The error amp gains the error from the false summing junction
by 10, and it contains a gain vernier to fine trim the gain.
11
12
3
4
5
10
+
AD841
+V
S
6
–V
S
2.2µF
0.1µF
R
L
INPUT
OUTPUT
100Ω
100Ω
11340-028
100
90
10
0%
10mV 5V 20ns
OUTPUT ERROR:
0.02%/DIV
OUTPUT:
5V/DIV
1
1340-029
DDD5109
FLAT-TOP
PULSE
GENERATOR
11
6
4
5
10
+
AD841
+15V
–15V
2.2µF
0.1µF
2.2µF
0.1µF
499Ω
50Ω
499Ω
1kΩ 1kΩ
1kΩ
1kΩ
ERROR
AMP
(×10)
TEK
7A13
TEK
7603
OSCILLOSCOPE
TEK
7A18
HP6263
FET PROBE
TEK P6201
11340-030
Data Sheet AD841
Rev. C | Page 11 of 16
Figure 31 shows the long-term stability of the settling charac-
teristics of the AD841 output after a 10 V step. There is no
evidence of settling tails after the initial transient recovery
time. The use of a junction isolated process, together with
careful layout, avoids these problems by minimizing the effects
of transistor isolation capacitance discharge and thermally
induced shifts in circuit operating points. These problems
do not occur even under high output current conditions.
Figure 31. AD841 Settling Demonstrating No Settling Tails
GROUNDING AND BYPASSING
In designing practical circuits with the AD841, the user must
remember that whenever high frequencies are involved, some
special precautions are in order. Circuits must be built with
short interconnect leads. Large ground planes should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Avoid sockets because the increased interlead
capacitance can degrade bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the circuit capacitances will not
limit the amplifier performance. Resistor values of less than
5 are recommended. If a larger resistor must be used, a
small (<10 pF) feedback capacitor in parallel with the feed-
back resistor, R
F
, may be used to compensate for these stray
capacitances and optimize the dynamic performance of the
amplifier in the particular application.
Bypass power supply leads to ground as close as possible to
the amplifier pins. A 2.2 µF capacitor in parallel with a 0.1 µF
ceramic disk capacitor is recommended.
CAPACITIVE LOAD DRIVING ABILITY
Like all wideband amplifiers, the AD841 is sensitive to capaci-
tive loading. The AD841 is designed to drive capacitive loads
of up to 20 pF without degradation of its rated performance.
Capacitive loads of greater than 20 pF will decrease the dynamic
performance of the part although instability should not occur
unless the load exceeds 100 pF (for a unity-gain follower). A
resistor in series with the output can be used to decouple larger
capacitive loads.
Figure 32 shows a typical configuration for driving a large
capacitive load. The 51 Ω output resistor effectively isolates the
high frequency feedback from the load and stabilizes the circuit.
Low frequency feedback is returned to the amplifier summing
junction via the low-pass filter formed by the 51 Ω resistor and
the load capacitance, C
L
.
Figure 32. Circuit for Driving a Large Capacitive Load
100
90
10
0%
500ns
OUTPUT ERROR:
0.02%/DIV
OUTPUT:
5V/DIV
11340-031
11
6
4
5
10
+
AD841
+V
S
–V
S
2.2µF
0.1µF
2.2µF
0.1µF
499Ω
1kΩ
15pF
1kΩ
INPUT
51Ω
C
L
R
L
V
OUT
11340-032

AD841JNZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers Wideband Unity-Gain Stable
Lifecycle:
New from this manufacturer.
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