DS1388Z-33+ Datasheet DS1388Z-33+, DS1388Z-5+, DS1388Z-3+ | P10-P12

DS1388

Clock Accuracy

The accuracy of the clock is dependent upon the accu-

racy of the crystal and the accuracy of the match

between the capacitive load of the oscillator circuit and

the capacitive load for which the crystal was trimmed.

Additional error is added by crystal frequency drift

caused by temperature shifts. External circuit noise

coupled into the oscillator circuit can result in the clock

running fast. Figure 3 shows a typical PC board layout

for isolation of the crystal and oscillator from noise.

Refer to Application Note 58:

Crystal Considerations

with Dallas Real-Time Clock

s for detailed information.

Address Map

Figure 4 shows the address map for the DS1388. The

memory map is divided into three blocks. The memory

block accessed is determined by the value of the block

address bits in the slave address byte. The timekeep-

ing registers reside in block 0h. During a multibyte

access of the timekeeping registers, when the internal

address pointer reaches 0Ch, it wraps around to loca-

tion 00h. On an I

C START or address pointer incre-

menting to location 00h, the current time is transferred

to a second set of registers. The time information is

read from these secondary registers, while the clock

may continue to run. This eliminates the need to reread

the registers in case the main registers update during a

read. The EEPROM is divided into two 256-byte blocks

located in blocks 1h and 2h. During a multibyte read of

the EEPROM registers, when the internal address point-

er reaches FFh, it wraps around to location 00h of the

block of EEPROM specified in the block address.

During a multibyte write of the EEPROM registers, when

the internal address pointer reaches the end of the cur-

rent 8-byte EEPROM page, it wraps around to the

beginning of the EEPROM page. See the

Write

Operation

section for details.

To avoid rollover issues when writing to the time and

date registers, all registers should be written before the

hundredths-of-seconds register reaches 99 (BCD).

Hundredths-of-Seconds

Generator

The hundredths-of-seconds generator circuit shown in

the

Block Diagram

is a state machine that divides the

incoming frequency (4096Hz) by 41 for 24 cycles and

40 for 1 cycle. This produces a 100Hz output that is

slightly off during the short term, and is exactly correct

every 250ms. The divide ratio is given by:

Ratio = [41 x 24 + 40 x 1] / 25 = 40.96

Thus, the long-term average frequency output is

exactly 100Hz.

C RTC/Supervisor with Trickle Charger

and 512 Bytes EEPROM

10 ____________________________________________________________________

LOCAL GROUND PLANE (LAYER 2)

CRYSTAL

GND

NOTE: AVOID ROUTING SIGNAL LINES

IN THE CROSSHATCHED AREA

(UPPER LEFT QUADRANT) OF

THE PACKAGE UNLESS THERE IS

A GROUND PLANE BETWEEN THE

SIGNAL LINE AND THE DEVICE PACKAGE.

Figure 3. Layout Example

DS1388

C RTC/Supervisor with Trickle Charger

and 512 Bytes EEPROM

____________________________________________________________________ 11

ADDRESS

BLK WORD

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE

0h 00h Tenth Seconds Hundredths of Seconds

Hundredths of

Seconds

00–99

0h 01h 0 10 Seconds Seconds Seconds 00–59

0h 02h 0 10 Minutes Minutes Minutes 00–59

AM/

10 Hour

0h 03h 0 12/24

10 Hour

Hours Hours

1–12+

AM/PM

00–23

0h 04h 0 0 0 0 X Day Day 01–07

0h 05h 0 0 10 Date Date Date 01–31

0h 06h 0 0 X

Month

Month Month 01–12

0h 07h 10 Year Year Year 00–99

0h 08h Watchdog Tenths of Seconds Watchdog Hundredths of Seconds

Watchdog

Hundredth

Seconds

00–99

0h 09h Watchdog Tenths of Seconds Watchdog Seconds

Watchdog

Seconds

00–99

0h 0Ah TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0 Trickle Charger —

0h 0Bh OSF WF 0 0 0 0 0 0 Flag —

0h 0Ch EOSC 0 0 0 0 0 WDE WD/RST Control —

1h 00–FFh 256 x 8 EEPROM EEPROM 00–FFh

2h 00–FFh 256 x 8 EEPROM EEPROM 00–FFh

Figure 4. Address Map

Note: Unless otherwise specified, the state of the registers is not defined when power (V

and V

BACKUP

) is first applied.

X = General-purpose read/write bit.

0 = Always reads as a zero.

Clock and Calendar

The time and calendar information is obtained by read-

ing the appropriate register bytes. Figure 4 illustrates

the RTC registers. The time and calendar are set or ini-

tialized by writing the appropriate register bytes. The

contents of the time and calendar registers are in the

binary-coded decimal (BCD) format. The end of the

month date is automatically adjusted for months with

fewer than 31 days, including corrections for leap years

through 2099. The day-of-week register increments at

midnight. Values that correspond to the day-of-week

are user-defined but must be sequential (i.e., if 1

equals Sunday, then 2 equals Monday, and so on).

Illogical time and date entries result in undefined oper-

ation. The DS1388 can be run in either 12-hour or 24-

hour mode. Bit 6 of the hours register is defined as the

12- or 24-hour mode-select bit. When high, the 12-hour

mode is selected. In the 12-hour mode, bit 5 is the

AM/PM bit with logic-high being PM. In the 24-hour

mode, bit 5 is the second 10-hour bit (20–23 hours).

Changing the 12/24 bit requires that the hours data be

re-entered in the proper format.

DS1388

Watchdog Alarm Counter

The contents of the watchdog alarm counter, which is a

separate two-byte BCD down counter, are accessed in

the address range 08h–09h in block 0h. It is programma-

ble in 10ms intervals from 0.01 to 99.99 seconds. When

this counter is written, both the counter and a seed regis-

ter are loaded with the desired value. When the counter is

to be reloaded, it uses the value in the seed register.

When the counter is read, the current counter value is

latched into a register, which is output on the serial data

line and the watchdog counter reloads the seed value.

If the counter is not needed, it can be disabled and

used as a 16-bit cache of battery-backed RAM by set-

ting the WDE bit in the control register to logic 0. If all

16 bits of the watchdog alarm counter are written to a

zero when WDE = 1, the counter is disabled and the

WF bit is not set.

When the WDE bit in the control register is set to a logic

1 and a non-zero value is written into the watchdog reg-

isters, the watchdog alarm counter decrements every

1/100 second, until it reaches zero. At this point, the WF

bit in the flag register is set. If WD/RST = 1, the RST pin

is pulsed low for t

RST

and access to the DS1388 is

inhibited. At the end of t

RST

, the RST pin becomes high

impedance, and read/write access to the DS1388 is

enabled. The WF flag remains set until cleared by writ-

ing WF to logic 0. The watchdog alarm counter can be

reloaded and restarted before the counter reaches zero

by reading or writing any of the watchdog alarm

counter registers.

The WF flag and WDE bit must be set to zero before writing

the watchdog registers. After writing the watchdog regis-

ters, WDE must be set to one to enable the watchdog.

Power-Up/Down, Reset, and

Pushbutton Reset Functions

A precision temperature-compensated reference and

comparator circuit monitors the status of V

. When an

out-of-tolerance condition occurs, an internal power-fail

signal is generated that blocks read/write access to the

device and forces the RST pin low. When V

returns

to an in-tolerance condition, the internal power-fail sig-

nal is held active for t

RST

to allow the power supply to

stabilize, and the RST pin is held low. If the EOSC bit is

set to a logic 1 (to disable the oscillator in battery-back-

up mode), the internal power-fail signal and the RST pin

are kept active for t

RST

plus the oscillator startup time.

Access is inhibited whenever RST is low.

The DS1388 provides for a pushbutton switch to be

connected to the RST output pin. When the DS1388 is

not in a reset cycle, it continuously monitors the RST

signal for a low-going edge. If an edge is detected, the

part debounces the switch by pulling the RST pin low

and inhibits read/write access. After the internal timer

has expired, the part continues to monitor the RST line.

If the line is still low, it continues to monitor the line look-

ing for a rising edge. Upon detecting release, the part

forces the RST pin low and holds it low for t

RST

Special-Purpose Registers

The DS1388 has three additional registers (control,

flag, and trickle charger) that control the real-time

clock, watchdog, and trickle charger.

Flag Register (00Bh)

Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit

indicates that the oscillator has stopped or was

stopped for some period of time and may be used to

judge the validity of the clock and calendar data. This

bit is edge triggered and is set to logic 1 when the

internal circuitry senses the oscillator has transitioned

from a normal run state to a STOP condition. The follow-

ing are examples of conditions that can cause the OSF

bit to be set:

1) The first time power is applied.

2) The voltage present on both V

and V

BACKUP

are

insufficient to support oscillation.

3) The EOSC bit is turned off.

4) External influences on the crystal (i.e., noise, leak-

age, etc.).

This bit remains at logic 1 until written to logic 0. This

bit can only be written to logic 0. Attempting to write

OSF to logic 1 leaves the value unchanged.

Bit 6: Watchdog Alarm Flag (WF). A logic 1 in this bit

indicates that the watchdog counter reached zero. If

WDE and WD/RST are set to 1, the RST pin pulses low

for t

RST

when the watchdog counter reaches zero and

sets WF = 1. At the completion of the pulse, the WF bit

remains set to logic 1. Writing this bit to logic 0 clears

the WF flag. This bit can only be written to logic 0.

Attempting to write logic 1 leaves the value unchanged.

Bits 5 to 0: These bits read as zero and cannot be

modified.

C RTC/Supervisor with Trickle Charger

and 512 Bytes EEPROM

12 ____________________________________________________________________

Flag Register (00Bh)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OSFWF000000

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

DS1388Z-33+

Mfr. #:

Buy DS1388Z-33+

Manufacturer:

Maxim Integrated

Description:

Real Time Clock I2C RTC/Supervisor w/Trickle Charger

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DS1388Z-33+

DS1388Z-33+

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