87974I Data Sheet
©2016 Integrated Device Technology, Inc Revision E January 26, 20164
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1, 15, 19,
24, 30, 35, 39,
43, 47, 51
GND Power Power supply ground.
2 nMR/OE Input Pullup
Active HIGH outputs enabled (active). When LOW, outputs are disabled
(High-impedance state) and reset of the device. During reset/output
disable the PLL feedback loop is open and the internal VCO is tied to its
lowest frequency. The 87974I requires reset after any loss of PLL lock.
Loss of PLL lock may occur when the external feedback path is interrupt-
ed. The length of the reset pulse should be greater than one reference
clock cycle (CLKx)
3 CLK_EN Input Pullup
Synchronizing clock enable. When HIGH, clock outputs QAx:QCx
are enabled. When LOW, clock outputs QAx:QCx are low.
LVCMOS / LVTTL interface levels.
4 SEL_B Input Pulldown
Selects divide value for Bank B output as described in Table 3D. LVCMOS
/ LVTTL interface levels.
5 SEL_C Input Pulldown
Selects divide value for Bank C output as described in Table 3D. LVCMOS
/ LVTTL interface levels.
6 PLL_SEL Input Pullup
Selects between the PLL and the reference clock as the input to the di-
viders. When HIGH, selects PLL. When LOW, selects the reference clock.
LVCMOS / LVTTL interface levels.
7 SEL_A Input Pulldown
Selects divide value for Bank A output as described in Table 3D. LVCMOS
/ LVTTL interface levels.
8 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
9 CLK0 Input Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
10 CLK1 Input Pullup Reference clock input. LVCMOS / LVTTL interface levels.
11, 27, 42 nc Unused No connect.
12 V
DD
Power Core supply pin.
13 V
DDA
Power Analog supply pin.
14, 20
FB_SEL0, FB_
SEL1
Input Pulldown
Selects divide value for Bank feedback output as described in
Table 3E. LVCMOS / LVTTL interface levels.
16, 18,
21, 23, 25
QA4, QA3,
QA2, QA1, QA0
Output
Bank A clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
17, 22, 26 V
DDOA
Power Output supply pins for Bank A clock outputs.
28 V
DDOFB
Power Output supply pin for QFB clock output.
29 QFB Output Clock output. LVCMOS / LVTTL interface levels.
31 FB_IN Input Pullup
Feedback input to phase detector for generating clocks with
“zero delay”. Connect to pin 29.
LVCMOS / LVTTL interface levels.
32, 34,
36, 38, 40
QB4, QB3,
QB2, QB1, QB0
Output
Bank B clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
33, 37, 41 V
DDOB
Power Output supply pins for Bank B clock outputs.
44, 46,
48, 50
QC3, QC2, QC1,
QC0
Output
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
45, 49 V
DDOC
Power Output supply pins for Bank C clock outputs.
52 VCO_SEL Input Pulldown
Selects VCO ÷ 4 when HIGH. Selects VCO ÷ 2 when LOW.
LVCMOS / LVTTL interface levels.
NOTE:
Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
