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AD524ARZ-16

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
AD524
Rev. F | Page 15 of 28
THEORY OF OPERATION
The AD524 is a monolithic instrumentation amplifier based
on the classic 3-op amp circuit. The advantage of monolithic
construction is the closely matched components that enhance
the performance of the input preamplifier. The preamplifier
section develops the programmed gain by the use of feedback
concepts. The programmed gain is developed by varying the
value of R
G
(smaller values increase the gain) while the feedback
forces the collector currents (Q1, Q2, Q3, and Q4) to be constant,
which impresses the input voltage across R
G
.
As R
G
is reduced to increase the programmed gain, the
transconductance of the input preamplifier increases to the
transconductance of the input transistors. This has three
important advantages. First, this approach allows the circuit
to achieve a very high open-loop gain of 3 × 10
8
at a programmed
gain of 1000, thus reducing gain-related errors to a negligible
30 ppm. Second, the gain bandwidth product, which is deter-
mined by C3 or C4 and the input transconductance, reaches
25 MHz. Third, the input voltage noise reduces to a value
determined by the collector current of the input transistors
for an RTI noise of 7 nV/√Hz at G = 1000.
INPUT PROTECTION
As interface amplifiers for data acquisition systems, instru-
mentation amplifiers are often subjected to input overloads,
that is, voltage levels in excess of the full scale for the selected
gain range. At low gains (10 or less), the gain resistor acts as a
current limiting element in series with the inputs. At high gains,
the lower value of R
G
does not adequately protect the inputs
from excessive currents. Standard practice is to place series
limiting resistors in each input, but to limit input current to
below 5 mA with a full differential overload (36 V) requires
over 7k of resistance, which adds 10 nV√Hz of noise. To
provide both input protection and low noise, a special series
protection FET is used.
A unique FET design was used to provide a bidirectional
current limit, thereby protecting against both positive and
negative overloads. Under nonoverload conditions, three
channels (CH
2
, CH
3
, CH
4
) act as a resistance (≈1 kΩ) in series
with the input as before. During an overload in the positive
direction, a fourth channel, CH
1
, acts as a small resistance
(≈3 kΩ) in series with the gate, which draws only the leakage
current, and the FET limits I
DSS
. When the FET enhances under
a negative overload, the gate current must go through the small
FET formed by CH
1
and when this FET goes into saturation,
the gate current is limited and the main FET goes into controlled
enhancement. The bidirectional limiting holds the maximum
input current to 3 mA over the 36 V range.
INPUT OFFSET AND OUTPUT OFFSET
Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may
be adjusted to zero, shifts in offset voltage due to temperature
variations causes errors. Intelligent systems can often correct
this factor with an autozero cycle, but there are many small-
signal high-gain applications that do not have this capability.
+V
s
RG
2
AD712
1/2
9.09kΩ
1kΩ
100Ω
16.2kΩ
1/2
16.2kΩ
1.62MΩ
1.82kΩ
10
100
1000
G = 1, 10, 100
G = 1000
AD524
+
V
S
–
+
–V
S
1
16
13
12
9
11
10
6
3
8
7
2
1µF
1µF
–V
S
1µF
3
2
8
1
5
6
4
7
0
0500-033
+
–
+
–
Figure 33. Noise Test Circuit
AD524
Rev. F | Page 16 of 28
Voltage offset and drift comprise two components each; input
and output offset and offset drift. Input offset is the component
of offset that is directly proportional to gain, that is, input offset
as measured at the output at G = 100 is 100 times greater than at
G = 1. Output offset is independent of gain. At low gains, output
offset drift is dominant, at high gains, input offset drift dominates.
Therefore, the output offset voltage drift is normally specified as
drift at G = 1 (where input effects are insignificant), whereas
input offset voltage drift is given by drift specification at a high
gain (where output offset effects are negligible). All input
related numbers are referred to the input (RTI) that is the effect
on the output is G times larger. Voltage offset vs. power supply
is also specified at one or more gain settings and is also RTI.
By separating these errors, one can evaluate the total error
independent of the gain setting used. In a given gain configura-
tion, both errors can be combined to give a total error referred
to the input (RTI) or output (RTO) by the following formulas:
Total error RTI = input error + (output error/gain)
Total error RTO = (gain × input error) + output error
As an illustration, a typical AD524 might have a +250 µV
output offset and a −50 µV input offset. In a unity gain
configuration, the total output offset would be 200 µV or
the sum of the two. At a gain of 100, the output offset would
be −4.75 mV or: +250 µV + 100(−50 µV) = −4.75 mV.
The AD524 provides for both input and output offset adjustment.
This simplifies very high precision applications and minimizes
offset voltage changes in switched gain applications. In such
applications, the input offset is adjusted first at the highest
programmed gain, then the output offset is adjusted at G = 1.
GAIN
The AD524 has internal high accuracy pretrimmed resistors
for pin programmable gains of 1, 10, 100, and 1000. One of the
preset gains can be selected by pin strapping the appropriate
gain terminal and RG
2
together (for G = 1, RG
2
is not connected).
AD524
G = 10
G = 100
G = 1000
+INPUT
–
INPUT
V
OUT
OUTPUT
SIGNAL
COMMON
–V
S
INPUT
OFFSET
NULL
+V
S
10kΩ
RG
1
RG
2
1
16
13
12
11
3
2
8
4
5
10
9
6
7
00500-034
Figure 34. Operating Connections for G = 100
The AD524 can be configured for gains other than those that
are internally preset; there are two methods to do this. The first
method uses just an external resistor connected between
Pin 3 and Pin 16 (see Figure 35), which programs the gain
according to the following formula:
1
k40
−=
Ω
=
G
R
G
For best results, R
G
should be a precision resistor with a low
temperature coefficient. An external R
G
affects both gain
accuracy and gain drift due to the mismatch between it and
the internal thin-film resistors. Gain accuracy is determined
by the tolerance of the external R
G
and the absolute accuracy
of the internal resistors (±20%). Gain drift is determined by the
mismatch of the temperature coefficient of R
G
and the tempera-
ture coefficient of the internal resistors (−50 ppm/°C typical).
40,000
2.105
G = + 1 = 20 ±20%
AD524
REFERENCE
1kΩ
+INPUT
–INPUT
2.105kΩ
1.5kΩ
V
OUT
+
V
S
–V
S
RG
1
RG
2
1
16
8
7
6
9
10
13
12
11
3
2
00500-035
Figure 35. Operating Connections for G = 20
The second method uses the internal resistors in parallel with
an external resistor (see Figure 36). This technique minimizes
the gain adjustment range and reduces the effects of tempera-
ture coefficient sensitivity.
G =
G = 10
AD524
REFERENCE
+INPUT
–INPUT
4kΩ
*R|
G = 10
= 4444.44Ω
*R|
G = 100
= 404.04Ω
*R|
G = 1000
= 40.04Ω
*NOMINAL (±20%)
V
OUT
40,000
4000||4444.44
+ 1 = 20 ±17%
+
V
S
–V
S
RG
1
RG
2
1
16
13
12
11
3
2
8
7
10
6
9
00500-036
Figure 36. Operating Connections for G = 20, Low Gain
Temperature Coefficient Technique
AD524
Rev. F | Page 17 of 28
The AD524 can also be configured to provide gain in the output
stage. Figure 37 shows an H pad attenuator connected
to the reference and sense lines of the AD524. R1, R2, and R3
should be made as low as possible to minimize the gain variation
and reduction of CMRR. Varying R2 precisely sets the gain
without affecting CMRR. CMRR is determined by the match
of R1 and R3.
G = 100
G = 1000
G =
G = 10
AD524
+INPUT
–INPUT
+V
S
–V
S
(R1 + R2 + R3)||R
L
≥ 2kΩ
V
OU
T
R
L
R1
2.26kΩ
R2
5kΩ
R3
2.26kΩ
(R2||40kΩ) + R1 + R3
(R2||40kΩ)
RG
1
RG
2
1
16
13
12
11
3
2
8
7
10
6
9
00500-037
Figure 37. Gain of 2000
Table 4. Output Gain Resistor Values
Output Gain R2 R1, R3 Nominal Gain
2 5 kΩ 2.26 kΩ 2.02
5 1.05 kΩ 2.05 kΩ 5.01
10 1 kΩ 4.42 kΩ 10.1
INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the
input transistors of a dc amplifier. Bias currents are an
additional source of input error and must be considered in
a total error budget. The bias currents, when multiplied by
the source resistance, appear as an offset voltage. What is of
concern in calculating bias current errors is the change in bias
current with respect to signal voltage and temperature. Input
offset current is the difference between the two input bias
currents. The effect of offset current is an input offset voltage
whose magnitude is the offset current times the source
impedance imbalance.
AD524
LOAD
+
–
TO POWER
SUPPLY
GROUND
+V
S
–V
S
2
3
11
12
13
16
1
8
7
10
6
9
00500-038
Figure 38. Indirect Ground Returns for Bias Currents—Transformer Coupled
AD524
LOAD
+
–
+V
S
–V
S
TO POWER
SUPPLY
GROUND
2
8
7
10
6
9
3
11
12
13
16
1
00500-039
Figure 39. Indirect Ground Returns for Bias Currents—Thermocouple
AD524
LOAD
+
V
S
–V
S
TO POWER
SUPPLY
GROUND
2
8
7
10
6
9
3
11
12
13
16
1
+
–
00500-040
Figure 40. Indirect Ground Returns for Bias Currents–AC-Coupled
Although instrumentation amplifiers have differential inputs,
there must be a return path for the bias currents. If this is not
provided, those currents charge stray capacitances, causing the
output to drift uncontrollably or to saturate. Therefore, when
amplifying floating input sources such as transformers and
thermocouples, as well as ac-coupled sources, there must still
be a dc path from each input to ground.
COMMON-MODE REJECTION
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance. Common-mode
rejection ratio (CMRR) is a ratio expression whereas common-
mode rejection (CMR) is the logarithm of that ratio. For
example, a CMRR of 10,000 corresponds to a CMR of 80 dB.
In an instrumentation amplifier, ac common-mode rejection is
only as good as the differential phase shift. Degradation of ac
common-mode rejection is caused by unequal drops across
differing track resistances and a differential phase shift due
to varied stray capacitances or cable capacitances. In many
applications, shielded cables are used to minimize noise. This
technique can create common-mode rejection errors unless the
shield is properly driven. Figure 41 and Figure 42 show active
data guards that are configured to improve ac common-mode
rejection by bootstrapping the capacitances of the input cabling,
thus minimizing differential phase shift.
REFERENCE
AD524
100Ω
AD711
G = 100
+INPUT
–INPUT
V
OUT
+
V
S
–V
S
+
–
RG
2
1
12
3
2
8
10
9
6
7
00500-041
Figure 41. Shield Driver, G ≥ 100
REFERENCE
AD524
100Ω
AD712
+INPUT
–INPUT
100Ω
V
OUT
+V
S
–V
S
RG
1
RG
2
–V
S
–
+
1
16
12
3
2
7
6
9
10
8
00500-042
Figure 42. Differential Shield Driver
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AD524ARZ-16

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