MIC2550A Micrel, Inc.
M9999-031805 4 March 2005
Symbol Parameter Condition Min Typ Max Units
Transceiver DC Characteristics
I
LO
Hi-Z State Data Line Leakage 0V < V
BUS
< 3.3V, D+, D–, OE# = 1 pins only –10 +10 µA
V
DI
Differential Input Sensitivity |(D+) – (D–)|, V
IN
= 0.8V – 2.5V 0.2 V
V
CM
Differential Common-Mode Range Includes V
DI
range 0.8 2.5 V
V
SE
Single-Ended Receiver Threshold 0.8 2.0 V
Receiver Hysteresis, Note 6 200 mV
V
OL
Static Output Low, Note 5 OE# = 0, R
L
= 1.5k to 3.6V 0.3 V
V
OH
Static Output High, Note 5 OE# = 0, R
L
= 15k to GND 2.8 3.6 V
V
CRS
Output Signal Crossover Voltage 1.3 2.0 V
Note 6
C
IN
Transceiver Capacitance, Note 6 Pin to GND 20 pF
Z
DRV
Driver Output Resistance Steady state drive, Note 6 618
Low-Speed Driver Characteristics, Note 7
t
R
Transition Rise Time C
L
= 50pF 75 ns
C
L
= 600pF 300 ns
t
F
Transition Fall Time C
L
= 50pF 75 ns
C
L
= 600pF 300 ns
t
R
/t
F
Rise and Fall Time Matching T
R
÷ T
F
80 125 %
V
CRS
Output Signal Crossover Voltage 1.3 2.0 V
Full-Speed Driver Characteristics, Note 7
t
R
Transition Rise Time C
L
= 50pF 4 20 ns
t
F
Transition Fall Time C
L
= 50pF 4 20 ns
t
R
/t
F
Rise and Fall Time Matching T
R
÷ T
F
90 111.11 %
V
CRS
Output Signal Crossover Voltage 1.3 2.0 V
Transceiver Timing, Note 7
t
PVZ
OE# to RCVR Tri-state Delay Figure 1 15 ns
t
PZD
Receiver Tri-state to Transmit Delay Figure 1 15 ns
t
PDZ
OE# to DRVR Tri-state Delay Figure 1 15 ns
t
PZV
Driver Tri-state to Receiver Delay Figure 1 15 ns
t
PLH
V+/V– to D+/D– Propagation Delay Figure 4 15 ns
t
PHL
V+/V– to D+/D– Propagation Delay Figure 4 15 ns
t
PLH
D+/D– to RCV Propagation Delay Figure 3 15 ns
t
PHL
D+/D– to RCV Propagation Delay Figure 3 15 ns
t
PLH
D+/D– to V+/D– Propagation Delay Figure 3 8 ns
t
PHL
D+/D– to V+/D– Propagation Delay Figure 3 8 ns
Note 1. Exceeding the absolute maximum rating may damage the device.
Note 2. The device is not guaranteed to function outside its operating rating.
Note 3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
Note 4. Applies to the VP, VM, RCV, OE#, SPD, and SUS pins.
Note 5. Applies to D+, D–.
Note 6. Not production tested. Guaranteed by design.
Note 7. Characterized specification(s), but not production tested.
March 2005 5 M9999-031805
MIC2550A Micrel, Inc.
V
M
V
P
V
P
/V
M
t
PVZ
t
PZV
V
OE#
H
L
t
PZD
V
D+
/V
D–
V
D–
V
D+
Figure 1. Enable and Disable Times
10%
V
D–
V
D+
Differential
Data
Lines
90%
t
R
t
F
V
CRS
Figure 2. Rise and Fall Times
V
D–
V
D+
Differential
Data
Lines
t
PLH
t
PHL
Output
V
OH
V
OL
V
SS
Figure 3. Receiver Propagation Delay D+/D– to RCV, V
P
, and V
M
V
D–
V
D+
Differential
Data
Lines
t
PLH
t
PHL
Input
V
OI
V
OL
V
SS
Figure 4. Driver Propagation Delay V
P
and V
M
to D+/D–
Timing Diagrams
MIC2550A Micrel, Inc.
M9999-031805 6 March 2005
:)timsnarT(0=#EO
tupnItuptuO
tluseRPVMV+D–DVCR
0000X 0ES
01010 0cigoL
10101 1cigoL
1111X denifednU
:)evieceR(1=#EO
tupnItuptuO
tluseR+D–DPVMVVCR
0000X 0ES
01010 0cigoL
10101 1cigoL
1111X denifednU
Note. X = undefined.
Table 1. Truth Table
Test Circuits
Device
Under
Test
50pF
24
For D+, D–:
V = 0V for t
PZH
and t
PHZ
V = V
BUS
for t
PZL
and t
PLZ
V
Test
Point
500
Figure 5. Load for Enable and Disable Time (D+, D–)
Device
Under
Test
25pF
Figure 6. V
P
, V
M
and RCV Load
Device
Under
Test
15k C
L
V
TRM
1.5k*
24
C
L
= 50pF, full speed
C
L
= 50pF, low speed (minimum timing)
C
L
= 600pF, low speed (maximum timing)
*1.5k on D– for low speed or D+ for high speed
Figure 7. D+ and D– Load

MIC2550AYTS

Mfr. #:
Manufacturer:
Microchip Technology / Micrel
Description:
USB Interface IC USB Transceiver
Lifecycle:
New from this manufacturer.
Delivery:
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