74LVC4T3144
4-bit dual supply buffer/line driver; 3-state
Rev. 1 — 14 August 2017 Product data sheet
1 General description
The 74LVC4T3144 is a 4-bit, dual-supply level translating buffer with 3-state outputs. It
features four data inputs (An and B4), four data outputs (YBn and YA4), and an output
enable input (OE). The device is configured to translate three inputs from V
CC(A)
to V
CC(B)
and one input from V
CC(B)
to V
CC(A)
. OE, An and YA4 are referenced to V
CC(A)
and YBn
and B4 are referenced to V
CC(B)
. A HIGH on OE causes the outputs to assume a high-
impedance OFF-state.
The device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables outputs, preventing any damaging backflow current through the device
when it is powered down. In suspend mode when either V
CC(A)
or V
CC(B)
are at GND
level, all outputs are in the high-impedance OFF-state.
2 Features and benefits
• Wide supply voltage range:
– V
CC(A)
: 1.2 V to 5.5 V
– V
CC(B)
: 1.2 V to 5.5 V
• High noise immunity
• Complies with JEDEC standards:
– JESD8-11A (1.4 V to 1.6 V)
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8C (3.0 V to 3.6 V)
– JESD12-6 (4.5 V to 5.5 V)
• ESD protection:
– HBM JESD22-A114F Class 3A exceeds 4000 V
– CDM JESD22-C101E exceeds 1000 V
• Maximum data rates:
– 200 Mbps (3.3 V to 5.0 V translation)
– 140 Mbps (translate to 3.3 V))
– 100 Mbps (translate to 2.5 V)
– 75 Mbps (translate to 1.8 V)
– 60 Mbps (translate to 1.5 V)
• Suspend mode
• Latch-up performance exceeds 100 mA per JESD 78B Class II
• ±24 mA output drive (V
CC
= 3.0 V)
• Inputs accept voltages up to 5.5 V
• Low power consumption: 30 μA maximum I
CC
• I
OFF
circuitry provides partial Power-down mode operation
• Specified from -40 °C to +85 °C and -40 °C to +125 °C
