IDT
™
/ ICS
™
PCI EXPRESS™ JITTER ATTENUATOR 8 ICS874003AGI-02 REV A MAY 1, 2013
ICS874003I-02
PCI EXPRESS™ JITTER ATTENUATOR
FIGURE 3C. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3B. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the V
PP
and V
CMR
input requirements. Figures 3A to 3D show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
FIGURE 3A. CLK/NCLK INPUT DRIVEN BY
ICS LVHSTL DRIVER
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in
Figure 3A,
the input termination applies for ICS LVHSTL
drivers. If you are using an LVHSTL driver from another vendor,
use their termination recommendation.
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVDS
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
R1
50Ω
R2
50Ω
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
LVHSTL
IDT
LVHSTL Driver
Differential
Input
CLK
nCLK
Differential
Input
LVPECL
3.3V
Zo = 50Ω
Zo = 50Ω
3.3V
R1
50Ω
R2
50Ω
R2
50Ω
.
L
n
L
.
.
LVPE
Diff
r
nti
l
In
u
3.3V
R1
100Ω
LVDS
CLK
nCLK
3.3V
Receiver
Zo = 50Ω
Zo = 50Ω