74LV00_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 20 December 2007 4 of 14
NXP Semiconductors
74LV00
Quad 2-input NAND gate
8. Recommended operating conditions
[1] The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
9. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
V
CC
supply voltage
[1]
1.0 3.3 5.5 V
V
I
input voltage 0 - V
CC
V
V
O
output voltage 0 - V
CC
V
T
amb
ambient temperature 40 +25 +125 °C
t/V input transition rise and fall rate V
CC
= 1.0 V to 2.0 V - - 500 ns/V
V
CC
= 2.0 V to 2.7 V - - 200 ns/V
V
CC
= 2.7 V to 3.6 V - - 100 ns/V
V
CC
= 3.6 V to 5.5 V - - 50 ns/V
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ
[1]
Max Min Max
V
IH
HIGH-level input voltage V
CC
= 1.2 V 0.9 - - 0.9 - V
V
CC
= 2.0 V 1.4 - - 1.4 - V
V
CC
= 2.7 V to 3.6 V 2.0 - - 2.0 - V
V
CC
= 4.5 V to 5.5 V 0.7V
CC
- - 0.7V
CC
-V
V
IL
LOW-level input voltage V
CC
= 1.2 V - - 0.3 - 0.3 V
V
CC
= 2.0 V - - 0.6 - 0.6 V
V
CC
= 2.7 V to 3.6 V - - 0.8 - 0.8 V
V
CC
= 4.5 V to 5.5 V - - 0.3V
CC
- 0.3V
CC
V
V
OH
HIGH-level output voltage V
I
= V
IH
or V
IL
I
O
= 100 µA; V
CC
= 1.2 V - 1.2 - - - V
I
O
= 100 µA; V
CC
= 2.0 V 1.8 2.0 - 1.8 - V
I
O
= 100 µA; V
CC
= 2.7 V 2.5 2.7 - 2.5 - V
I
O
= 100 µA; V
CC
= 3.0 V 2.8 3.0 - 2.8 - V
I
O
= 100 µA; V
CC
= 4.5 V 4.3 4.5 - 4.3 - V
I
O
= 6 mA; V
CC
= 3.0 V 2.4 2.82 - 2.2 - V
I
O
= 12 mA; V
CC
= 4.5 V 3.6 4.2 - 3.5 - V
74LV00_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 20 December 2007 5 of 14
NXP Semiconductors
74LV00
Quad 2-input NAND gate
[1] Typical values are measured at T
amb
= 25 °C.
10. Dynamic characteristics
[1] All typical values are measured at T
amb
=25°C.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] Typical values are measured at nominal supply voltage (V
CC
= 3.3 V and V
CC
= 5.0 V).
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+Σ(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz, f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
N = number of inputs switching
Σ(C
L
× V
CC
2
× f
o
) = sum of the outputs.
V
OL
LOW-level output voltage V
I
= V
IH
or V
IL
I
O
= 100 µA; V
CC
= 1.2 V - 0 - - - V
I
O
= 100 µA; V
CC
= 2.0 V - 0 0.2 - 0.2 V
I
O
= 100 µA; V
CC
= 2.7 V - 0 0.2 - 0.2 V
I
O
= 100 µA; V
CC
= 3.0 V - 0 0.2 - 0.2 V
I
O
= 100 µA; V
CC
= 4.5 V - 0 0.2 - 0.2 V
I
O
= 6 mA; V
CC
= 3.0 V - 0.25 0.40 - 0.50 V
I
O
= 12 mA; V
CC
= 4.5 V - 0.35 0.55 - 0.65 V
I
I
input leakage current V
I
=V
CC
or GND; V
CC
= 5.5 V - - 1.0 - 1.0 µA
I
CC
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
- - 20.0 - 40 µA
I
CC
additional supply current per input; V
I
= V
CC
0.6 V;
V
CC
= 2.7 V to 3.6 V
- - 500 - 850 µA
C
I
input capacitance - 3.5 - - - pF
Table 6. Static characteristics
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ
[1]
Max Min Max
Table 7. Dynamic characteristics
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter Conditions 40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ
[1]
Max Min Max
t
pd
propagation delay nA, nB to nY; see Figure 6
[2]
V
CC
= 1.2 V - 45 - - - ns
V
CC
= 2.0 V - 15 26 - 31 ns
V
CC
= 2.7 V - 11 18 - 23 ns
V
CC
= 3.0 V to 3.6 V; C
L
=15pF
[3]
-7- - -ns
V
CC
= 3.0 V to 3.6 V
[3]
- 9.0 15 - 18 ns
V
CC
= 4.5 V to 5.5 V
[3]
- 6.5 11 - 14 ns
C
PD
power dissipation
capacitance
C
L
= 50 pF; f
i
= 1 MHz;
V
I
= GND to V
CC
[4]
-22- - -pF
74LV00_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 20 December 2007 6 of 14
NXP Semiconductors
74LV00
Quad 2-input NAND gate
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6. The input (nA, nB) to output (nY) propagation delays
001aah088
t
PHL
t
PLH
V
M
V
M
nY output
nA, nB input
V
I
GND
V
OH
V
OL
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
M
V
M
< 2.7 V 0.5V
CC
0.5V
CC
2.7 V to 3.6 V 1.5 V 1.5 V
4.5 V 0.5V
CC
0.5V
CC
Test data is given in Table 9.
Definitions test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
Fig 7. Load circuit for switching times
V
CC
V
I
V
O
001aaa663
D.U.T.
C
L
50 pF
R
T
R
L
1 k
PULSE
GENERATOR
Table 9. Test data
Supply voltage Input
V
CC
V
I
t
r
, t
f
< 2.7 V V
CC
2.5 ns
2.7 V to 3.6 V 2.7 V 2.5 ns
4.5 V V
CC
2.5 ns

74LV00N,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Logic Gates QUAD 2-INPUT NAND
Lifecycle:
New from this manufacturer.
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