Note 1: Tested at V
DD
= 5.0V; single-ended, unipolar.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Grounded on-channel; sine wave applied to all off channels.
Note 4: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: The common-mode range for the analog inputs is from AGND to V
DD
.
Note 7: Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: Measured at V
SUPPLY
+ 5% and V
SUPPLY
- 5% only.
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V ±5%, f
CLK
= 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,
T
A
= T
MIN
to T
MAX,
unless otherwise noted. Typical values are at T
A
= +25°C.)
I
SINK
= 16mA
I
SINK
= 5mA
SHDN = open
SHDN = open
SHDN = 0V
SHDN = V
DD
(Note 5)
V
IN
= 0V or V
DD
CONDITIONS
V
0.3
V
OL
Output Voltage Low
0.4
nA-100 100
SHDN Max Allowed Leakage,
Mid Input
V2.75V
FLT
SHDN Voltage, Floating
V1.5 V
DD
- 1.5V
IM
SHDN Input Mid Voltage
µA-4.0I
INL
SHDN Input Current, Low
µA4.0I
INH
SHDN Input Current, High
V0.5V
INL
SHDN Input Low Voltage
VV
DD
- 0.5V
INH
SHDN Input High Voltage
pF15C
IN
DIN,SCLK, CS Input Capacitance
µA±1I
IN
DIN, SCLK, CS Input Leakage
V0.15V
HYST
DIN, SCLK, CS Input Hysteresis
V0.8V
INL
DIN,SCLK, CS Input Low Voltage
V2.4V
INH
DIN,SCLK, CS Input High Voltage
UNITSMIN TYP MAXSYMBOLPARAMETER
Output Voltage High V
OH
I
SOURCE
= 1mA 4 V
Three-State Leakage Current I
L
CS = 5V
±10 µA
Three-State Leakage Capacitance C
OUT
CS = 5V (Note 5)
15 pF
Positive Supply Voltage V
DD
5 ±5% V
Operating mode 1.5 2.5 mA
Fast power-down 30 70Positive Supply Current I
DD
Full power-down 2 10
µA
Positive Supply Rejection
(Note 9)
PSR
V
DD
= 5V ±5%; external reference, 4.096V;
full-scale input
±0.06 ±0.5 mV
EXTERNAL REFERENCE AT REFADJDIGITAL INPUTS (DIN, SCLK,
–
C
—
S
–
,
–
S
—
H
—
D
—
N
–
)
DIGITAL OUTPUTS (DOUT, SSTRB)
POWER REQUIREMENTS