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7025L20PFGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
6.42
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
10
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. t
BDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last
tABE, tAOE, tACE, tAA or tBDD.
5. SEM = V
IH.
Waveform of Read Cycles
(5)
Timing of Power-Up Power-Down
t
RC
R/W
CE
ADDR
t
AA
OE
UB, LB
2683 drw 07
(4)
t
ACE
(4)
t
AOE
(4)
t
ABE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
CE
2683 drw 08
t
PU
I
CC
I
SB
t
PD
50%
50%
.
6.42
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
11
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
IL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the
entire t
EW time.
4. The specification for t
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual t
DH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
Symbol Parameter
7025X15
Com'l Only
7025X17
Com'l Only
7025X20
Com'l, Ind
& Military
7025X25
Com'l &
Military
UnitMin. Max. Min. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 15
____
17
____
20
____
25
____
ns
t
EW
Chip Enable to End-of-Write
(3 )
12
____
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write 12
____
12
____
15
____
20
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
12
____
15
____
20
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 10
____
10
____
15
____
15
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10
____
12
____
15 ns
t
DH
Data Hold Time
(4 )
0
____
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
10
____
10
____
12
____
15 ns
t
OW
Output Active from End-of-Write
(1, 2,4 )
0
____
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
5
____
ns
t
SP S
SEM Flag Contention Window
5
____
5
____
5
____
5
____
ns
2683 tbl 13a
Symbol Parameter
7025X35
Com'l &
Military
7025X55
Com'l, Ind
& Military
7025X70
Military Only
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 35
____
55
____
70
____
ns
t
EW
Chip Enable to End-of-Write
(3 )
30
____
45
____
50
____
ns
t
AW
Address Valid to End-of-Write 30
____
45
____
50
____
ns
t
AS
Address Set-up Time
(3 )
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 25
____
40
____
50
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 15
____
30
____
40
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
25
____
30 ns
t
DH
Data Hold Time
(4 )
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
15
____
25
____
30 ns
t
OW
Output Active from End-of-Write
(1 , 2,4)
0
____
0
____
0
____
ns
t
SWR D
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
2683 tbl 13b
6.42
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
12
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
(1,5,8)
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing
(1,5)
NOTES:
1. R/W or CE or UB & LB = V
IH during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of a UB or LB = VIL and a CE = VIL and a R/W = VIL for memory array writing cycle.
3. t
WR is measured from the earlier of CE or R/W (or SEM or R/W) going to VIH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW = V
IL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the HIGH impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W, or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load
(Figure 2).
8. If OE = V
IL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t
DW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t
WP.
9. To access RAM, CE = V
IL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be met
for either condition.
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4) (4)
(7)
UB or LB
2683 drw 09
(9)
CE or SEM
(9)
(7)
(3)
2683 drw 10
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
UB or LB
(3)
(2)
(6)
CE or SEM
(9)
(9)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

7025L20PFGI

Mfr. #:
Buy 7025L20PFGI
Manufacturer:
IDT
Description:
SRAM 8K X 16 DP SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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