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7025L20PFI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
6.42
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
13
SEM
2683 drw 11
t
AW
t
EW
t
SOP
DATA
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID
DATA
OUT
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
t
SOP
Read Cycle
Write Cycle
A
0
-A
2
OE
VALID
(2)
Timing Waveform of Semaphore Read after Write Timing, Either Side
(1)
NOTE:
1. CE = V
IH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. "DATA
OUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
NOTES:
1. D
OR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W
"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If t
SPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
Timing Waveform of Semaphore Write Contention
(1,3,4)
SEM
"A"
2683 drw 12
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE
"A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE
(2)
"B"
6.42
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write Port-to-Port Read and BUSY (M/S = V
IH)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention with Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention with Port "A".
6. 'X' in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range
(6)
7025X15
Com'l Ony
7025X17
Com'l Only
7025X20
Com'l, Ind
& Military
7025X25
Com'l &
Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (M/S = V
IH
)
t
BAA
BUSY Access Time from Address Match
____
15
____
17
____
20
____
20 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
15
____
17
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enable LOW
____
15
____
17
____
20
____
20 ns
t
BDC
BUSY Disable Time from Chip Enable HIGH
____
15
____
17
____
17
____
17 ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
18
____
18
____
30
____
30 ns
t
WH
Write Hold After BUSY
(5)
12
____
13
____
15
____
17
____
ns
BUSY TIMING (M/S = V
IL
)
t
WB
BUSY Input to Write
(4)
0
____
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
12
____
13
____
15
____
17
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
30
____
30
____
45
____
50 ns
t
DD D
Write Data Valid to Read Data Delay
(1 )
____
25
____
25
____
35
____
35 ns
2683 tbl 14a
7025X35
Com'l &
Military
7025X55
Com'l, Ind
& Military
7025X70
Military Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (M/S = V
IH
)
t
BAA
BUSY Access Time from Address Match
____
20
____
45
____
45 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
20
____
40
____
40 ns
t
BAC
BUSY Access Time from Chip Enable LOW
____
20
____
40
____
40 ns
t
BDC
BUSY Disable Time from Chip Enable HIGH
____
20
____
35
____
35 ns
t
APS
Arbitration Priority Set-up Time
(2 )
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
35
____
40
____
45 ns
t
WH
Write Hold After BUSY
(5 )
25
____
25
____
25
____
ns
BUSY TIMING (M/S = V
IL
)
t
WB
BUSY Input to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5 )
25
____
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
60
____
80
____
95 ns
t
DD D
Write Data Valid to Read Data Delay
(1 )
____
45
____
65
____
80 ns
2683 tbl 14b
6.42
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
15
Timing Waveform of Write Port-to-Port Read and BUSY
(2,4,5)
(M/S = VIH)
Timing Waveform of Write with BUSY
NOTES:
1. t
WH must be met for both BUSY input (slave) output master.
2. BUSY is asserted on port "B" Blocking R/W
"B", until BUSY"B" goes HIGH.
3. t
WB is only for the 'Slave' Version.
2683 drw 13
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
t
BAA
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS is ignored for M/S = VIL (slave).
2. CE
L = CER = VIL.
3. OE = V
IL for the reading port.
4. If M/S = V
IL (SLAVE), then BUSY is an input. Therefore in this example BUSY"A" = VIH and BUSY"B" input is shown.
5. All timing is the same for left and right ports. Port "A" may be either the left of right port. Port "B" is the opposite port from Port "A".
2683 drw 14
R/W
"A"
BUS Y
"B"
t
WP
t
WB
R/W
"B"
t
WH
(1)
(2)
(3)
.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

7025L20PFI

Mfr. #:
Buy 7025L20PFI
Manufacturer:
IDT
Description:
SRAM 8KX16 DUAL PORT
Lifecycle:
New from this manufacturer.
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