6.42
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
11
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
IL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the
entire t
EW time.
4. The specification for t
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual t
DH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
Symbol Parameter
7025X15
Com'l Only
7025X17
Com'l Only
7025X20
Com'l, Ind
& Military
7025X25
Com'l &
Military
UnitMin. Max. Min. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 15
____
17
____
20
____
25
____
ns
t
EW
Chip Enable to End-of-Write
(3 )
12
____
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write 12
____
12
____
15
____
20
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
12
____
15
____
20
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 10
____
10
____
15
____
15
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10
____
12
____
15 ns
t
DH
Data Hold Time
(4 )
0
____
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
10
____
10
____
12
____
15 ns
t
OW
Output Active from End-of-Write
(1, 2,4 )
0
____
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
5
____
ns
t
SP S
SEM Flag Contention Window
5
____
5
____
5
____
5
____
ns
2683 tbl 13a
Symbol Parameter
7025X35
Com'l &
Military
7025X55
Com'l, Ind
& Military
7025X70
Military Only
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 35
____
55
____
70
____
ns
t
EW
Chip Enable to End-of-Write
(3 )
30
____
45
____
50
____
ns
t
AW
Address Valid to End-of-Write 30
____
45
____
50
____
ns
t
AS
Address Set-up Time
(3 )
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 25
____
40
____
50
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 15
____
30
____
40
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
25
____
30 ns
t
DH
Data Hold Time
(4 )
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
15
____
25
____
30 ns
t
OW
Output Active from End-of-Write
(1 , 2,4)
0
____
0
____
0
____
ns
t
SWR D
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
2683 tbl 13b