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DS2764AE+025

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface
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BL2—EEPROM Block 2 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 2 (addresses 40 to 47) is
locked (read-only) while a 0 indicates block 2 is unlocked (read/write). The special order unique 64-bit ID device
does not support EEPROM Block 2.
BL1—EEPROM Block 1 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 1 (addresses 30 to 3F) is
locked (read-only) while a 0 indicates block 1 is unlocked (read/write).
BL0—EEPROM Block 0 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 0 (addresses 20 to 2F) is
locked (read-only) while a 0 indicates block 0 is unlocked (read/write).
X—Reserved Bits.
SPECIAL FEATURE REGISTER
The format of the special feature register is shown in Figure 14. The function of each bit is described in detail in the
following paragraphs.
Figure 14. Special Feature Register Format
ADDRESS 08
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PS
X X X X X SAWE X
PSPS Pin Latch. This bit latches a low state on the PS pin with a 0 value. The bit is cleared only by writing a 1 to
this location. See the Power Switch Input section.
SAWESlave Address Write Enable. This bit must be set to 1 before the 2-wire slave address in location 0x32 can
be modified. SAWE should be written back to 0 after writing the slave address. Power up default is 0.
XReserved Bits.
PROGRAMMABLE SLAVE ADDRESS
The 2-Wire slave address of the DS2764 is stored in lockable EEPROM block 1, address 32h. Programming the
slave address requires a write to set the SAWE bit in the Special Feature register, followed by a write to 32h with
the desired slave address. The new slave address value is effective following the write to 32h, and must be used
to address the DS2764 on subsequent bus transactions. The slave address value is not stored to EEPROM until a
Copy EEPROM block 1 command is executed. Prior to executing the Copy command, power cycling the DS2764
restores the original slave address value. The data format of the slave address value in address 32h is shown in
Figure 15.
Figure 15. Slave Address Format
ADDRESS 32
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
A6 A5 A4 A3 A2 A1 A0 X
A6 to A0—Slave Address. A6-A0 contains the 7-bit slave address of the DS2764. The factory default is
0110100b.
X—Reserved Bits.
DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface
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2-WIRE BUS SYSTEM
The 2-Wire bus system supports operation as a slave only device in a single or multi-slave, and single or multi-
master system. Up to 128 slave devices may share the bus by uniquely setting the 7-bit slave address. The 2-wire
interface consists of a serial data line (SDA) and serial clock line (SCL). SDA and SCL provide bidirectional
communication between the DS2764 slave device and a master device at speeds up to 100kHz. The DS2764’s
SDA pin operates bi-directionally, that is, when the DS2764 receives data, SDA operates as an input, and when the
DS2764 returns data, SDA operates as an open drain output, with the host system providing a resistive pull-up.
The DS2764 always operates as a slave device, receiving and transmitting data under the control of a master
device. The master initiates all transactions on the bus and generates the SCL signal as well as the START and
STOP bits which begin and end each transaction.
Bit Transfer
One data bit is transferred during each SCL clock cycle, with the cycle defined by SCL transitioning low-to-high and
then high-to-low. The SDA logic level must remain stable during the high period of the SCL clock pulse. Any
change in SDA when SCL is high is interpreted as a START or STOP control signal.
Bus Idle
The bus is defined to be idle, or not busy, when no master device has control. Both SDA and SCL remain high
when the bus is idle. The STOP condition is the proper method to return the bus to the idle state.
START and STOP Conditions
The master initiates transactions with a START condition (S), by forcing a high-to-low transition on SDA while SCL
is high. The master terminates a transaction with a STOP condition (P), a low-to-high transition on SDA while SCL
is high. A Repeated START condition (Sr) can be used in place of a STOP then START sequence to terminate
one transaction and begin another without returning the bus to the idle state. In multi-master systems, a Repeated
START allows the master to retain control of the bus. The START and STOP conditions are the only bus activities
in which the SDA transitions when SCL is high.
Acknowledge Bits
Each byte of a data transfer is acknowledged with an Acknowledge bit (A) or a No Acknowledge bit (N). Both the
master and the DS2764 slave generate acknowledge bits. To generate an Acknowledge, the receiving device
must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until
SCL returns low. To generate a No Acknowledge (also called NAK), the receiver releases SDA before the rising
edge of the acknowledge-related clock pulse and leaves SDA high until SCL returns low. Monitoring the
acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer can occur if a
receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus
master should re-attempt communication.
Data Order
A byte of data consists of 8 bits ordered most significant bit (msb) first. The least significant bit (lsb) of each byte is
followed by the Acknowledge bit. DS2764 registers composed of multi-byte values are ordered most significant
byte (MSB) first. The MSB of multi-byte registers is stored on even data memory addresses.
Slave Address
A bus master initiates communication with a slave device by issuing a START condition followed by a Slave
Address (SAddr) and the read/write (R/W) bit. When the bus is idle, the DS2764 continuously monitors for a
START condition followed by its slave address. When the DS2764 receives a slave address that matches the
value in its Programmable Slave Address register, it responds with an Acknowledge bit during the clock period
following the R/W bit. The 7-bit Programmable Slave Address register is factory programmed to 0110100. The
slave address can be re-programmed, refer to the Programmable Slave Address section for details.
Read/Write Bit
The R/W bit following the slave address determines the data direction of subsequent bytes in the transfer. R/W = 0
selects a write transaction, with the following bytes being written by the master to the slave. R/W = 1 selects a
read transaction, with the following bytes being read from the stave by the master.
DS2764 High-Precision Li+ Battery Monitor With 2-Wire Interface
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Bus Timing
The DS2764 is compatible with any bus timing up to 100kHz. No special configuration is required to operate at any
speed.
2-Wire Command Protocols
The command protocols involve several transaction formats. The simplest format consists of the master writing the
START bit, slave address, R/W bit, and then monitoring the acknowledge bit for presence of the DS2764. More
complex formats such as the Write Data, Read Data and Function command protocols write data, read data and
execute device specific operations. All bytes in each command format require the slave or host to return an
Acknowledge bit before continuing with the next byte. Each function command definition outlines the required
transaction format. The following key applies to the transaction formats.
Table 3. 2-Wire Protocol Key
KEY DESCRIPTION KEY DESCRIPTION
S START bit Sr Repeated START
SAddr Slave Address (7-bit) W R/W bit = 0
FCmd Function Command byte R R/W bit = 1
MAddr Memory Address byte P STOP bit
Data Data byte written by master Data Data byte returned by slave
A Acknowledge bit - Master A
Acknowledge bitSlave
N No Acknowledge - Master N
No AcknowledgeSlave
Basic Transaction Formats
Write: S SAddr W A MAddr A Data0 A P
A write transaction transfers one or more data bytes to the DS2764. The data transfer begins at the memory
address supplied in the MAddr byte. Control of the SDA signal is retained by the master throughout the
transaction, except for the Acknowledge cycles.
Read: S SAddr W A MAddr A Sr SAddr R A Data0 N P
Write Portion Read Portion
A read transaction transfers one or more bytes from the DS2764. Read transactions are composed of two parts, a
write portion followed by a read portion, and is therefore inherently longer than a write transaction. The write
portion communicates the starting point for the read operation. The read portion follows immediately, beginning
with a Repeated START, Slave Address with R/W set to a 1. Control of SDA is assumed by the DS2764 beginning
with the Slave Address Acknowledge cycle. Control of the SDA signal is retained by the DS2764 throughout the
transaction, except for the Acknowledge cycles. The master indicates the end of a read transaction by responding
to the last byte it requires with a No Acknowledge. This signals the DS2764 that control of SDA is to remain with
the master following the Acknowledge clock.
Write Data Protocol
The write data protocol is used to write to register and shadow RAM data to the DS2764 starting at memory
address MAddr. Data0 represents the data written to MAddr, Data1 represents the data written to MAddr + 1 and
DataN represents the last data byte, written to MAddr + N. The master indicates the end of a write transaction by
sending a STOP or Repeated START after receiving the last acknowledge bit.
S SAddr W A MAddr A Data0 A Data1 A … DataN A P
The msb of the data to be stored at address MAddr can be written immediately after the MAddr byte is
acknowledged. Because the address is automatically incremented after the least significant bit (lsb) of each byte is
received by the DS2764, the msb of the data at address MAddr + 1 is can be written immediately after the
acknowledgement of the data at address MAddr. If the bus master continues an auto-incremented write
transaction beyond address 4Fh, the DS2764 ignores the data. Data is also ignored on writes to read-only
addresses and reserved addresses, locked EEPROM blocks as well as a write that auto increments to the Function
Command register (address FEh). Incomplete bytes and bytes that are Not Acknowledged by the DS2764 are not
written to memory. As noted in the Memory Section, writes to unlocked EEPROM blocks modify the shadow RAM
only.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

DS2764AE+025

Mfr. #:
Buy DS2764AE+025
Manufacturer:
Maxim Integrated
Description:
Battery Management Ic Mon Batt Li-Ion Hp
Lifecycle:
New from this manufacturer.
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