HI7190IBZ Datasheet HI7190IBZ, HI7190IBZ-T, HI7190IPZ | P16-P18

FN3612.10

June 27, 2006

first SCLK transition output is delayed 29 OSC

cycles from

the next rising OSC

. SCLK transitions eight times and then

stalls high for 28 OSC

cycles. After this stall period is

completed SCLK will again transition eight times and stall

high. This sequence will repeat continuously while CS

active.

The extra OSC

cycle required when coming out of the CS

inactive state is a one clock cycle latency required to

properly sample the CS

input. Note that the normal stall at

byte boundaries is 28 OSC

cycles thus giving a SCLK rising

to rising edge stall period of 32 OSC

cycles.

The affects of CS on the I/O are different for self-clocking

mode (MODE = 1) than for external mode (MODE = 0). For

external clocking mode CS

inactive disables the I/O state

machine, effectively freezing the state of the I/O cycle. That

is, an I/O cycle can be interrupted using chip select and the

HI7190 will continue with that I/O cycle when re-enabled via

. SCLK can continue toggling while CS is inactive. If CS

goes inactive during an I/O cycle, it is up to the user to

ensure that the state of SCLK is identical when reactivating

as to what it was when CS went inactive. For read

operations in external clocking mode, the output will go

three-state immediately upon deactivation of CS

For self-clocking mode (MODE = 1), the affects of CS are

different. If CS transitions high (inactive) during the period

when data is being transferred (any non stall time) the HI7190

will complete the data transfer to the byte boundary. That is,

once SCLK begins the eight transition sequence, it will always

complete the eight cycles. If CS remains inactive after the byte

has been transferred it will be sampled and SCLK will remain

stalled high indefinitely. If CS has returned to active low before

the data byte transfer period is completed the HI7190 acts as

if CS was active during the entire transfer period.

It is important to realize that the user can interrupt a data

transfer on byte boundaries. That is, if the Instruction

is inactive after

only one byte has been transferred, the HI7190, when

reactivated, will continue with the remaining two bytes before

looking for the next Instruction Register write cycle.

Note that the outputs will NOT go three-state immediately upon

CS inactive for read operations in self-clocking mode. In the

case of CS going inactive during a read cycle the outputs

remain driving until after the last data bit is transferred. In the

case of CS inactive during the clock stall time it takes 1 OSC

cycle plus prop delay (Max) for the outputs to be disabled.

I/O Port Pin Descriptions

The serial I/O port is a bidirectional port which is used to

read the data register and read or write the control register

and calibration registers. The port contains two data lines, a

synchronous clock, and a status flag. Figure 11 shows a

diagram of the serial interface lines.

SDO - Serial Data out. Data is read from this line using those

protocols with separate lines for transmitting and receiving

data. An example of such a standard is the Motorola Serial

Peripheral Interface (SPI) using the 68HC05 and 68HC11

family of microcontrollers, or other similar processors. In the

case of using bidirectional data transfer on SDIO, SDO does

not output data and is set in a high impedance state.

SDIO - Serial Data in or out. Data is always written to the

device on this line. However, this line can be used as a

bidirectional data line. This is done by properly setting up the

Control Register. Bidirectional data transfer on this line can

be used with Intel standard serial interfaces (SSR, Mode 0)

in MCS51 and MCS96 family of microcontrollers, or other

similar processors.

SCLK - Serial clock. The serial clock pin is used to

synchronize data to and from the HI7190 and to run the port

state machines. In Synchronous External Clock Mode, SCLK

is configured as an input, is supplied by the user, and can

run up to a 5MHz rate. In Synchronous Self Clocking Mode,

SCLK is configured as an output and runs at OSC

/8.

CS - Chip select. This signal is an active low input that allows

more than one device on the same serial communication lines.

The SDO and SDIO will go to a high impedance state when this

signal is high. If driven high during any communication cycle,

that cycle will be suspended until CS

reactivation. Chip select

can be tied low in systems that maintain control of SCLK.

CHIP SELECT

SDO

SDIO

SCLK

DRDY

HI7190

DEVICE STATUS

BIDIRECTIONAL DATA

DATA OUT

PORT CLOCK

MODECLOCK MODE

FIGURE 11. HI7190 SERIAL INTERFACE

OSC

SCLK

29 33 37 41

121 125

FIGURE 12. SCLK OUTPUT IN SELF-CLOCKING MODE

HI7190

FN3612.10

June 27, 2006

DRDY - Data Ready. This is an output status flag from the

device to signal that the Data Output Register has been

updated with the new conversion result. DRDY is useful as an

edge or level sensitive interrupt signal to a microprocessor or

microcontroller. DRDY low indicates that new data is available

at the Data Output Register. DRDY will return high upon

completion of a complete Data Output Register read cycle.

MODE - Mode. This input is used to select between

Synchronous Self Clocking Mode (‘1’) or the Synchronous

External Clocking Mode (‘0’). When this pin is tied to V

the

serial port is configured in the Synchronous Self Clocking

mode where the synchronous shift clock (SCLK) for the serial

port is generated by the HI7190 and has a frequency of

OSC

/8. When the pin is tied to DGND the serial port is

configured for the Synchronous External Clocking Mode

where the synchronous shift clock for the serial port is

generated by an external device up to a maximum frequency

of 5MHz.

Programming the Serial Interface

It is useful to think of the HI7190 interface in terms of

communication cycles. Each communication cycle happens

in 2 phases. The first phase of every communication cycle

is the writing of an instruction byte. The second phase is

the data transfer as described by the instruction byte. It is

important to note that phase 2 of the communication cycle

can be a single byte or a multi-byte transfer of data. For

example, the 3-byte Data Output Register can be read

using one multi-byte communication cycle rather than three

single-byte communication cycles. It is up to the user to

maintain synchronism with respect to data transfers. If the

system processor “gets lost” the only way to recover is to

reset the HI7190. Figures 13A and 13B show both a 2-wire

and a 3-wire data transfer.

Several formats are available for reading from and writing to

the HI7190 registers in both the 2-wire and 3-wire protocols.

A portion of these formats is controlled by the CR<2:1> (BD

and MSB

) bits which control the byte direction and bit order

of a data transfer respectively. These two bits can be written

in any combination but only the two most useful will be

discussed here.

The first combination is to reset both the BD and MSB bits

(BD = 0, MSB = 0). This sets up the interface for descending

byte order and MSB first format. When this combination is

used the user should always write the Instruction Register

such that the starting byte is the most significant byte

address. For example, read three bytes of DR starting with

the most significant byte. The first byte read will be the most

significant in MSB to LSB format. The next byte will be the

next least significant (recall descending byte order) again in

MSB to LSB order. The last byte will be the next lesser

significant byte in MSB to LSB order. The entire word was

read MSB to LSB format.

The second combination is to set both the BD and MSB

bits

to 1. This sets up the interface for ascending byte order and

LSB first format. When this combination is used the user

should always write the Instruction Register such that the

starting byte is the least significant byte address. For

example, read three bytes of DR starting with the least

significant byte. The first byte read will be the least

significant in LSB to MSB format. The next byte will be the

next greater significant (recall ascending byte order) again in

LSB to MSB order. The last byte will be the next greater

significant byte in LSB to MSB order. The entire word was

read MSB to LSB format.

After completion of each communication cycle, The HI7190

interface enters a standby mode while waiting to receive a

new instruction byte.

Instruction Byte Phase

The instruction byte phase initiates a data transfer

sequence. The processor writes an 8-bit byte (Instruction

Byte) to the Instruction Register. The instruction byte informs

the HI7190 about the Data transfer phase activities and

includes the following information:

• Read or Write cycle

• Number of Bytes to be transferred

• Which register and starting byte to be accessed

Data Transfer Phase

In the data transfer phase, data transfer takes place as set

by the Instruction Register contents. See Write Operation

and Read Operation sections for detailed descriptions.

INSTRUCTION

BYTE

DATA

BYTE 1

DATA

BYTE 2

DATA

BYTE 3

INSTRUCTION

DATA TRANSFER

CYCLE

SDIO

FIGURE 13A. 2-WIRE, 3-BYTE READ OR WRITE TRANSFER

INSTRUCTION

BYTE

DATA

BYTE 1

DATA

BYTE 2

DATA

BYTE 3

INSTRUCTION

DATA TRANSFER

CYCLE

SDIO

SDO

FIGURE 13B. 3-WIRE, 3-BYTE READ TRANSFER

HI7190

FN3612.10

June 27, 2006

Instruction Register

The Instruction Register is an 8-bit register which is used

during a communications cycle for setting up read/write

operations.

R/W - Bit 7 of the Instruction Register determines whether a

read or write operation will be done following the instruction

byte load. 0 = READ, 1 = WRITE.

MB1, MB0 - Bits 6 and 5 of the Instruction Register

determine the number of bytes that will be accessed

following the instruction byte load. See Table 5 for the

number of bytes to transfer in the transfer cycle.

FSC - Bit 4 is used to determine whether a Positive Full Scale

Calibration Register I/O transfer (FSC = 0) or a Negative Full

Scale Calibration Register I/O transfer (FSC = 1) is being

performed (see Table 6).

A3, A2, A1, A0 - Bits 3 and 2 (A3 and A2) of the Instruction

while bits 1 and 0 (A1 and A0) determine which byte of that

decode.

Write Operation

Data can be written to the Control Register, Offset

Calibration Register, Positive Full Scale Calibration Register,

and the Negative Full Scale Calibration Register. Write

operations are done using the SDIO, CS

and SCLK lines

only, as all data is written into the HI7190 via the SDIO line

even when using the 3-wire configuration. Figures 14 and 15

show typical write timing diagrams.

The communication cycle is started by asserting the CS

line

low and starting the clock from its idle state. To assert a write

cycle, during the instruction phase of the communication

cycle, the Instruction Byte should be set to a write transfer

/W = 1).

When writing to the serial port, data is latched into the

HI7190 on the rising edge of SCLK. Data can then be

changed on the falling edge of SCLK. Data can also be

changed on the rising edge of SCLK due to the 0ns hold time

required on the data. This is useful in pipelined applications

where the data is latched on the rising edge of the clock.

Read Operation - 3-Wire Transfer

Data can be read from the Data Output Register, Control

Calibration Register, and the Negative Full Scale Calibration

operations are done using the SDIO, SDO, CS

and SCLK

lines. All data is read via the SDO line. Figures 16 and 17

show typical 3-wire read timing diagrams.

The communication cycle is started by asserting the CS

line

and starting the clock from its idle state. To assert a read

cycle, during the instruction phase of the communication

cycle, the Instruction Byte should be set to a read transfer

/W = 0).

When reading the serial port, data is driven out of the HI7190

on the falling edge of SCLK. Data can be registered

externally on the next rising edge of SCLK.

Read Operation - 2-Wire Transfer

Data can be read from the Data Output Register, Control

Calibration Register, and the Negative Full Scale Calibration

operations are done using the SDIO, CS

and SCLK lines. All

data is read via the SDIO line. Figures 18 and 19 show

typical 2-wire read timing diagrams.

INSTRUCTION REGISTER

MSB654321LSB

R/W MB1 MB0 FSC A3 A2 A1 A0

TABLE 5. MULTIPLE BYTE ACCESS BITS

MB1 MB0 DESCRIPTION

0 0 Transfer 1 Byte

0 1 Transfer 2 Bytes

1 0 Transfer 3 Bytes

1 1 Transfer 4 Bytes

TABLE 6. INTERNAL DATA ACCESS DECODE STARTING

BYTE

FSCA3A2A1A0 DESCRIPTION

X 0000Data Output Register, Byte 0

X 0001Data Output Register, Byte 1

X 0010Data Output Register, Byte 2

X 0100Control Register, Byte 0

X 0101Control Register, Byte 1

X 0110Control Register, Byte 2

X 1000Offset Cal Register, Byte 0

X 1001Offset Cal Register, Byte 1

X 1010Offset Cal Register, Byte 2

0 1100Positive Full Scale Cal Register, Byte 0

0 1101Positive Full Scale Cal Register, Byte 1

0 1110Positive Full Scale Cal Register, Byte 2

1 1100Negative Full Scale Cal Register, Byte 0

1 1101Negative Full Scale Cal Register, Byte 1

1 1110Negative Full Scale Cal Register, Byte 2

TABLE 6. INTERNAL DATA ACCESS DECODE STARTING

BYTE (Continued)

FSCA3A2A1A0 DESCRIPTION

HI7190

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

HI7190IBZ

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Analog to Digital Converters - ADC ADC 24BIT 10MHZ SIGMADELTA 20 IND

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HI7190IBZ

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