MT8960/61/62/63/64/65/66/67 Data Sheet
19
Zarlink Semiconductor Inc.
AC Electrical Characteristics - Receive (D/A) Path - Voltages are with respect to GNDD unless otherwise stated.
T
A
=0 to 70°C, V
DD
=5V±5%, V
EE
=-5V±5%, V
Ref
=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz,
Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified.
Characteristics Sym. Min. Typ.* Max. Units Test Conditions
1
A
N
A
L
O
G
Analog output at V
R
equivalent to the overload
decision level at codec
V
OUT
4.829
5.000
V
pp
V
pp
Level at codec:
µ-Law: 3.17 dBm0
A-Law: 3.14 dBm0
R
L
=10 K
See Note 7
2 Absolute Gain (0dB setting) G
AR
-0.25 +0.25 dB 0 dBm0 @ 1004Hz
3 Absolute Attenuation (-1dB
to -7dB settings)
-0.35 +0.35 dB From nominal,
@ 1004Hz
4 Gain Variation With Temp. G
ART
0.01 dB T
A
=0°C to 70°C
With Supplies G
ARS
0.04 dB/V
5 Gain Tracking CCITT G712
(See Figure 12) (Method 1)
GT
R1
-0.25
-0.25
-0.50
+0.25
+0.25
+0.50
dB
dB
dB
Sinusoidal Level:
+3 to -10 dBm0
Noise Signal Level:
-10 to -55 dBm0
-55 to -60 dBm0
CCITT G712
(Method 2)
AT & T
GT
R2
-0.25
-0.50
-1.50
+0.25
+0.50
+1.50
dB
dB
dB
Sinusoidal Level:
+3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
6 Quantization CCITT G712
Distortion (Method 1)
(See Fig. 13)
D
QR1
28.00
35.60
33.90
29.30
14.30
dB
dB
dB
dB
dB
Noise Signal Level:
-3 dBm0
-6 to -27 dBm0
-34 dBm0
-40 dBm0
-55 dBm0
CCITT G712
(Method 2)
AT & T
D
QR2
36.40
30.40
25.40
dB
dB
dB
Sinusoidal Input Level:
0 to -30 dBm0
-40 dBm0
-45 dBm0
7 Idle Channel C-message N
CR
12 dBrnC0 µ-Law Only
Noise Psophometric N
PR
-75 dBm0p CCITT G712
8 Single Frequency Noise N
SFR
-56 dBm0 CCITT G712
9 Harmonic Distortion
(2nd or 3rd Harmonic)
-46 dB Input Signal 0 dBm0
at 1.02 kHz
10 Intermodulation CCITT G712
Distortion 2 tone
IMD
R2
-41 dB
AT & T IMD
R3
-47 dB 2nd order products
4 tone IMD
R4
-49 dB 3rd order products
MT8960/61/62/63/64/65/66/67 Data Sheet
20
Zarlink Semiconductor Inc.
* Typical figures are at 25
°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.
Note 7: 0dBm0=1.185 V
RMS
for µ-Law codec and 0dBm0=1.231 V
RMS
for A-Law codec.
11
A
N
A
L
O
G
Envelope Delay D
AR
210 µs @ 1004 Hz
12 Envelope Delay 1000-2600 Hz
Variation with 600-3000 Hz
Frequency 400-3200 Hz
D
DR
90
170
265
µs
µs
µs
Input Signal:
400 - 3200 Hz digital
sinewave at 0 dBm0
13 Gain Relative to <200 Hz
Gain @ 1004 Hz 200 Hz
(See Figure 11) 300-3000 Hz
3300 Hz
3400 Hz
4000 Hz
4600 Hz
G
RR
-0.5
-0.125
-0.350
-0.80
0.125
0.125
0.125
0.030
-0.100
-14.0
-28.0
dB
dB
dB
dB
dB
dB
dB
0 dBm0 Input Signal
Receive
Filter
Response
14 Crosstalk A/D to D/A CT
TR
-70 dB 0 dBm0 @ 1.02 kHz
in A/D
15 Power Supply V
DD
Rejection V
EE
PSRR
3
PSRR
4
33
35
dB
dB
Input 50 mV
RMS
at
1.02 kHz
16 Overload Distortion
(See Fig. 15)
Input frequency=1.02
kHz
AC Electrical Characteristics - Receive (D/A) Path
- Voltages are with respect to GNDD unless otherwise stated.
T
A
=0 to 70°C, V
DD
=5V±5%, V
EE
=-5V±5%, V
Ref
=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz,
Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified.
MT8960/61/62/63/64/65/66/67 Data Sheet
21
Zarlink Semiconductor Inc.
Figure 9a - Timing Diagram - 125 µs Frame Period
C2i
INPUT
F1i
INTERNAL
ENABLE
DSTo
OUTPUT
DSTi
INPUT
CA
CSTi
INPUT
LOAD
A-REGISTER
LOAD
B-REGISTER
125 µs
76543210 76543210
76543210
HIGH IMPEDANCE
7
7
76
6
76543210
5 V
0 V
(Mode 3)

MT8963ASR1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Telecom Interface ICs Pb Free CODEC A-LAW ALTERNATIVE CODECS
Lifecycle:
New from this manufacturer.
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