LTC3769
26
3769fa
For more information www.linear.com/LTC3769
APPLICATIONS INFORMATION
6. Keep the switching node (SW), top gate node (TG) and
boost node (BOOST) away from sensitive small-signal
nodes. All of these nodes have very large and fast moving
signals and, therefore, should be kept on the output side
of the LTC3769 and occupy a minimal PC trace area.
7. Use a modified “star ground” technique: a low imped
-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV
CC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the GND pins of the IC.
PC Board Layout Debugging
It is helpful to use a DC-50MHz current probe to monitor
the current in the inductor while testing the circuit. Moni
-
tor the output switching node (SW pin) to synchronize
the oscilloscope to the internal oscillator and probe the
actual output voltage. Check for proper performance over
the operating voltage and current range expected in the
application. The frequency of operation should be main
-
tained over the input voltage range down to dropout and
until the output load drops below the low current opera-
tion
threshold— typically 10% of the maximum designed
current level in Burst Mode operation.
T
h
e duty cycle percentage should be maintained from cycle
to cycle in a well designed, low noise PCB implementa
-
tion. Variation in the duty cycle at a subharmonic rate can
suggest noise pickup at the current or voltage sensing
inputs
or
inadequate loop compensation. Overcompensa-
tion of the loop can be used to tame a poor PC layout if
regulator bandwidth optimization is not required.
Reduce V
IN
from its nominal level to verify operation with
high duty cycle. Check the operation of the undervoltage
lockout circuit by further lowering V
IN
while monitoring
the outputs to verify operation.
Investigate whether any problems exist only at higher out
-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling.
An embarrassing problem which can be missed in an oth
-
erwise properly working switching regulator, results when
the current sensing leads are hooked up backwards. The
output voltage under this improper hook-up
will still be
maintained, but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
