AT87F51RC-24JC Datasheet AT87F51RC-24PI, AT87F51RC-24AC, AT87F51RC-24AI | P7-P9

AT87F51RC

Memory Organization

MCS-51 devices have a separate address space for Pro-

gram and Data Memory. Up to 64K bytes each of external

Program and Data Memory can be addressed.

Program Memory

If the EA pin is connected to GND, all program fetches are

directed to external memory.

On the AT87F51RC, if EA

is connected to V

, program

fetches to addresses 0000H through 7FFFH are directed to

internal memory and fetches to addresses 8000H through

FFFFH are to external memory.

Data Memory

The AT87F51RC has internal data memory that is mapped

into four separate segments: the lower 128 bytes of RAM,

upper 128 bytes of RAM, 128 bytes special function regis-

ter (SFR) and 256 bytes expanded RAM (ERAM).

The four segments are:

1. The Lower 128 bytes of RAM (addresses 00H to

7FH) are directly and indirectly addressable.

2. The Upper 128 bytes of RAM (addresses 80H to

FFH) are indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses

80H to FFH) are directly addressable only.

4. The 256-byte expanded RAM (ERAM, 00H-FFH) is

indirectly accessed by MOVX instructions, and with

the EXTRAM bit cleared.

The Lower 128 bytes can be accessed by either direct or

indirect addressing. The Upper 128 bytes can be accessed

by indirect addressing only. The Upper 128 bytes occupy

the same address space as the SFR. This means they

have the same address, but are physically separate from

the SFR space.

When an instruction accesses an internal location above

address 7FH, the CPU knows whether the access is to the

upper 128 bytes of data RAM or to SFR space by the

addressing mode used in the instruction. Instructions that

use direct addressing access SFR space. For example:

MOV 0A0H, # data

accesses the SFR at location 0S0H (which is P2). Instruc-

tions that use indirect addressing access the Upper 128

bytes of data RAM. For example:

MOV@R0, # data

where R0 contains 0A0H, accesses the data byte at

address 0A0H, rather than P2 (whose address is 0A0H).

Note that stack operations are examples of indirect

addressing, so the upper 128 bytes of data RAM are avail-

able as stack space.

The 256 bytes of ERAM can be accessed by indirect

addressing, with EXTRAM bit cleared and MOVX instruc-

tions. This part of memory is physically located on-chip,

logically occupying the first 256 bytes of external data

memory.

Figure 1. Internal and External Data Memory Address

(with EXTRAM = 0)

With EXTRAM = 0, the ERAM is indirectly addressed,

using the MOVX instruction in combination with any of the

registers R0, R1 of the selected bank or DPTR. An access

to ERAM will not affect ports P0, P2, P3.6 (WR

), and P3.7

(RD

). For example, with EXTRAM = 0,

MOVX@R0, # data

where R0 contains 0A0H, accesses the ERAM at address

0A0H rather than external memory. An access to external

data memory locations higher than FFH (i.e. 0100H to

FFFFH) will be performed with the MOVX DPTR instruc-

tions in the same way as in the standard MCS-51, i.e., with

P0 and P2 as data/address bus, and P3.6 and P3.7 as

write and read timing signals. Refer to Figure 1.

With EXTRAM = 1, MOVX @ Ri and MOVX@DPTR will be

similar to the standard MCS-51. MOVX@Ri will provide an

8-bit address multiplexed with data on Port 0 and any out-

put port pins can be used to output higher-order address

bits. This is to provide the external paging capability.

MOVX@DPTR will generate a 16-bit address. Port 2 out-

puts the high-order 8 address bits (the contents of DP0H),

while Port 0 multiplexes the low-order 8 address bits (the

contents of DP0L) with data. MOVX@Ri and

MOVX@DPTR will generate either read or write signals on

P3.6 (WR

) and P3.7 (RD).

The stack pointer (SP) may be located anywhere in the 256

bytes RAM (lower and upper RAM) internal data memory.

The stack may not be located in the ERAM.

ERAM

256 BYTES

UPPER

128 BYTES

INTERNAL

RAM

LOWER

128 BYTES

INTERNAL

RAM

SPECIAL

FUNCTION

EXTERNAL

DATA

MEMORY

0100

0000

AT87F51RC

Hardware Watchdog Timer

(One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations

where the CPU may be subjected to software upsets. The

WDT consists of a 14-bit counter and the WatchDog Timer

Reset (WDTRST) SFR. The WDT is defaulted to disable

from exiting reset. To enable the WDT, a user must write

01EH and 0E1H in sequence to the WDTRST register

(SFR location 0A6H). When the WDT is enabled, it will

increment every machine cycle while the oscillator is run-

ning. There is no way to disable the WDT except through

reset (either hardware reset or WDT overflow reset). When

WDT overflows, it will drive an output RESET HIGH pulse

at the RST pin.

Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in

sequence to the WDTRST register (SFR location 0A6H).

When the WDT is enabled, the user needs to service it by

writing 01EH and 0E1H to WDTRST to avoid a WDT over-

flow. The 14-bit counter overflows when it reaches 16383

(3FFFH), and this will reset the device. When the WDT is

enabled, it will increment every machine cycle while the

oscillator is running. This means the user must reset the

WDT at least every 16383 machine cycles. To reset the

WDT the user must write 01EH and 0E1H to WDTRST.

WDTRST is a write-only register. The WDT counter cannot

be read or written. When WDT overflows, it will generate an

output RESET pulse at the RST pin. The RESET pulse

duration is 98xTOSC, where TOSC=1/FOSC. To make the

best use of the WDT, it should be serviced in those sec-

tions of code that will periodically be executed within the

time required to prevent a WDT reset.

WDT During Power-down and Idle

In power-down mode the oscillator stops, which means the

WDT also stops. While in power-down mode, the user does

not need to service the WDT. There are two methods of

exiting power-down mode: by a hardware reset or via a

level-activated external interrupt which is enabled prior to

entering power-down mode. When power-down is exited

with hardware reset, servicing the WDT should occur as it

normally does whenever the AT87F51RC is reset. Exiting

power-down with an interrupt is significantly different. The

interrupt is held low long enough for the oscillator to stabi-

lize. When the interrupt is brought high, the interrupt is ser-

viced. To prevent the WDT from resetting the device while

the interrupt pin is held low, the WDT is not started until the

interrupt is pulled high. It is suggested that the WDT be

reset during the interrupt service for the interrupt used to

exit power-down.

To ensure that the WDT does not overflow within a few

states of exiting power-down, it is best to reset the WDT

just before entering power-down.

Before going into the IDLE mode, the WDIDLE bit in SFR

AUXR is used to determine whether the WDT continues to

count if enabled. The WDT keeps counting during IDLE

(WDIDLE bit = 0) as the default state. To prevent the WDT

from resetting the AT87F51RC while in IDLE mode, the

user should always set up a timer that will periodically exit

IDLE, service the WDT, and reenter IDLE mode.

With WDIDLE bit enabled, the WDT will stop to count in

IDLE mode and resumes the count upon exit from IDLE.

UART

The UART in the AT87F51RC operates the same way as

the UART in the AT89C51, AT89C52 and AT89C55. For

further information, see the December 1997 Microcontroller

Data Book, page 2-48, section titled, “Serial Interface”.

Timer 0 and 1

Timer 0 and Timer 1 in the AT87F51RC operate the same

way as Timer 0 and Timer 1 in the AT87F51 and AT87F52.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either

a timer or an event counter. The type of operation is

selected by bit C/T2

in the SFR T2CON (shown in Table 2).

Timer 2 has three operating modes: capture, auto-reload

(up or down counting), and baud rate generator. The

modes are selected by bits in T2CON, as shown in Table 4.

Timer 2 consists of two 8-bit registers, TH2 and TL2. In the

Timer function, the TL2 register is incremented every

machine cycle. Since a machine cycle consists of 12 oscil-

lator periods, the count rate is 1/12 of the oscillator fre-

quency.

In the Counter function, the register is incremented in

response to a 1-to-0 transition at its corresponding external

input pin, T2. In this function, the external input is sampled

during S5P2 of every machine cycle. When the samples

show a high in one cycle and a low in the next cycle, the

count is incremented. The new count value appears in the

Table 4. Timer 2 Operating Modes

RCLK +TCLK CP/RL2 TR2 MODE

0 0 1 16-bit Auto-reload

0 1 1 16-bit Capture

1 X 1 Baud Rate Generator

X X 0 (Off)

AT87F51RC

the transition was detected. Since two machine cycles (24

oscillator periods) are required to recognize a 1-to-0 transi-

tion, the maximum count rate is 1/24 of the oscillator fre-

quency. To ensure that a given level is sampled at least

once before it changes, the level should be held for at least

one full machine cycle.

Capture Mode

In the capture mode, two options are selected by bit

EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer

or counter which upon overflow sets bit TF2 in T2CON.

This bit can then be used to generate an interrupt. If

EXEN2 = 1, Timer 2 performs the same operation, but a 1-

to-0 transition at external input T2EX also causes the cur-

rent value in TH2 and TL2 to be captured into RCAP2H and

RCAP2L, respectively. In addition, the transition at T2EX

causes bit EXF2 in T2CON to be set. The EXF2 bit, like

TF2, can generate an interrupt. The capture mode is illus-

trated in Figure 2.

Auto-Reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when

configured in its 16-bit auto-reload mode. This feature is

invoked by the DCEN (Down Counter Enable) bit located in

the SFR T2MOD (see Table 5). Upon reset, the DCEN bit

is set to 0 so that timer 2 will default to count up. When

DCEN is set, Timer 2 can count up or down, depending on

the value of the T2EX pin.

Figure 2. Timer in Capture Mode

Figure 3 shows Timer 2 automatically counting up when

DCEN=0. In this mode, two options are selected by bit

EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to

0FFFFH and then sets the TF2 bit upon overflow. The

overflow also causes the timer registers to be reloaded with

the 16-bit value in RCAP2H and RCAP2L. The values in

Timer in Capture ModeRCAP2H and RCAP2L are preset

by software. If EXEN2 = 1, a 16-bit reload can be triggered

either by an overflow or by a 1-to-0 transition at external

input T2EX. This transition also sets the EXF2 bit. Both the

TF2 and EXF2 bits can generate an interrupt if enabled.

Setting the DCEN bit enables Timer 2 to count up or down,

as shown in Figure 3. In this mode, the T2EX pin controls

the direction of the count. A logic 1 at T2EX makes Timer 2

count up. The timer will overflow at 0FFFFH and set the

TF2 bit. This overflow also causes the 16-bit value in

RCAP2H and RCAP2L to be reloaded into the timer regis-

ters, TH2 and TL2, respectively.

A logic 0 at T2EX makes Timer 2 count down. The timer

underflows when TH2 and TL2 equal the values stored in

RCAP2H and RCAP2L. The underflow sets the TF2 bit and

causes 0FFFFH to be reloaded into the timer registers.

The EXF2 bit toggles whenever Timer 2 overflows or

underflows and can be used as a 17th bit of resolution. In

this operating mode, EXF2 does not flag an interrupt.

OSC

EXF2

T2EX PIN

T2 PIN

TR2

EXEN2

C/T2 = 0

C/T2 = 1

CONTROL

CAPTURE

OVERFLOW

CONTROL

TRANSITION

DETECTOR

TIMER 2

INTERRUPT

÷12

RCAP2LRCAP2H

TH2 TL2

TF2

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

AT87F51RC-24JC

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