MK1493-05
DIFFERENTIAL SPREAD SPECTRUM CLOCK DRIVER CLOCK SYNTHESIZER
IDT™
DIFFERENTIAL SPREAD SPECTRUM CLOCK DRIVER 7
MK1493-05 REV J 051310
Byte 6: Control Register
Notes:
1. These bits are read-only when the hardware/software bit is set to hardware control.
2. When the hardware/software bit is set to hardware control these bits reflect the state of the S[3:1] and SEL100/96#
pins and the SO bit is set to zero. When the hardware/software bit is set to software control the S[3:1] and SEL100/96# pins
are overridden by these bits.
3. See Spread Spectrum Selection Table on page 2 for spread selection options.
4. Use the same vendor ID as is used for the CK408 clock chip.
Power Down Mode Operation
The Power Down pin is used to shut off the clock cleanly prior to shutting off power to the device. The power down
pin is an active high asynchronous input. When PWRDWN is sampled low for two output clock periods then all
clocks need to be stopped prior to turning off the VCO. ALL clocks need to be stopped in a predictable manner.
CLKOUT is driven differentially when PWRDWN# is de-asserted unless the CLKOUT is disabled through the SMBus register
bit.
Bit Description Type Power Up Output(s) Affected Notes
7 Revision ID bit 3 R -- Not applicable
6 Revision ID bit 2 R -- Not applicable
5 Revision ID bit 1 R -- Not applicable
4 Revision ID bit 0 R -- Not applicable
3 Vendor ID bit 3 R -- Not applicable 4
2 Vendor ID bit 2 R -- Not applicable 4
1 Vendor ID bit 1 R -- Not applicable 4
0 Vendor ID bit 0 R -- Not applicable 4
CLKOUT/
CLKOUT
CLKIN
REFOUT
PWRDN
CLK VCO
ON OFF
TpHZ
MK1493-05
DIFFERENTIAL SPREAD SPECTRUM CLOCK DRIVER CLOCK SYNTHESIZER
IDT™
DIFFERENTIAL SPREAD SPECTRUM CLOCK DRIVER 8
MK1493-05 REV J 051310
CLKIN must have a stable clock input when PWRDN is de-asserted. If CLKIN starts after PWRDN is de-asserted then
Tstable specification applies to when CLKIN is ON. If CLKIN is full ON before PWRDN is de-asserted then the Tstable
specification applies.
CLKOUT
CLKOUT/
CLKIN
PWRDN/ De-Assertion, CLKIN Already Running
REFOUT
VDD
CLK VCO
PWRDN
OFF STARTING STABLE
Tstable
TpZH
CLKOUT/
CLKOUT
CLKIN
PWRDN/ De-Assertion, CLKIN Not Yet Running
REFOUT
VDD
CLK VCO
PWRDN
OFF STARTING STABLE
Tstable
TpZH
MK1493-05
DIFFERENTIAL SPREAD SPECTRUM CLOCK DRIVER CLOCK SYNTHESIZER
IDT™
DIFFERENTIAL SPREAD SPECTRUM CLOCK DRIVER 9
MK1493-05 REV J 051310
Application Information
Series Termination Resistor
Clock output traces should use series termination. To series
terminate a 50 trace (a commonly used trace impedance),
place a 33 resistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
MK1493-05 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) To minimize EMI, and obtain the best signal integrity, the
33 series termination resistor should be placed close to
the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the MK1493-05.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1493-05. These ratings are stress
ratings only. Functional operation of the device at these or any other conditions above those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Item Rating
Supply Voltage, VDD, VDDA 5.5 V
All Inputs and Outputs -0.5 V to VDD+0.5 V
Ambient Operating Temperature 0 to +70° C
Storage Temperature -65 to +150° C
Junction Temperature 125° C
Soldering Temperature 260° C
ESD Protection (Input) 2000 V min. (HBM)

MK1493-05GLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution DIFFERENTIAL SPREAD SPECTRUM CLK DRIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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