MK1493-05
DIFFERENTIAL SPREAD SPECTRUM CLOCK DRIVER CLOCK SYNTHESIZER
IDT™
DIFFERENTIAL SPREAD SPECTRUM CLOCK DRIVER 4
MK1493-05 REV J 051310
General SMBus Serial Interface
How to Write:
Controller (host) sends a start bit
Controller (host) sends the write address D4
(H)
IDT clock will acknowledge
Controller (host) sends the beginning byte location =N
IDT clock will acknowledge
Controller (host) sends the data byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte N + X - 1
(see Note 2)
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) sends a start bit
Controller (host) sends the write address D4
(H)
IDT clock will acknowledge
Controller (host) sends the beginning byte location =N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address D5
(H)
IDT clock will acknowledge
Controller (host) sends the data byte count = X
IDT clock sends Byte N + X - 1
IDT clock sends Byte 0 through byte X (if X
(H)
was written to
byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarTbit
Slave Address D4
H)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte = N .
X
B
Y
T
E
ACK
O
O O
O O
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarTbit
Slave Address D4
(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D5
(H)
RD
ReaD
ACK
Data Bye Count = X
ACK
.
X
B
Y
T
E
Beginning Byte N
ACK
O
O O
O O
O
Byte N + X - 1
N
Not acknowledge
PstoP bit
MK1493-05
DIFFERENTIAL SPREAD SPECTRUM CLOCK DRIVER CLOCK SYNTHESIZER
IDT™
DIFFERENTIAL SPREAD SPECTRUM CLOCK DRIVER 5
MK1493-05 REV J 051310
SMBus Address
The MK1493-05 is a slave-only device that supports block read and block write protocol using a single 7 bit address and
read/write bit. A block write (D4h) or block read (D5h) is made up of seven (7) bits and one (1) read/write bit.
The applications where the indexed block write and block
are used, the dummy byte (bit 11-18) functions as a
register-offset (8 bits) pointer.
Byte 0: Control Register
A6 A5 A4 A3 A2 A1 A0 R/W#
1101010X
Bit Description Type Power Up
Condition
Output(s) Affected Notes
7 Spread Select 0 RW 0 CLKOUT, CLKOUT 1,2,3
6 Spread Select 1 RW S1 CLKOUT, CLKOUT
1,2,3
5 Spread Select 2 RW S2 CLKOUT, CLKOUT
1,2,3
4 Spread Select 3 RW S3 CLKOUT, CLKOUT
1,2,3
3 Select Output Frequency,
1=100 MHz, 0=96 MHz
RW SEL 100/96
CLKOUT, CLKOUT 1,2
2 Reserved, must be written as 0 RW 0 Not applicable 1
1 Spread spectrum enable,
0=spread OFF, 1=spread ON
RW 1=spread ON CLKOUT, CLKOUT
1
0 Hardware/Software control of
spread enable, S[3:0], and
output frequency.
0=h.w cinttrol, 1=s/w control
RW 0=h/w control Not applicable
MK1493-05
DIFFERENTIAL SPREAD SPECTRUM CLOCK DRIVER CLOCK SYNTHESIZER
IDT™
DIFFERENTIAL SPREAD SPECTRUM CLOCK DRIVER 6
MK1493-05 REV J 051310
Byte 1: Control Register
Byte 2 through 5: Control
Bit Description Type Power Up
Condition
Output(s) Affected Notes
7 Reserved, must be written as 0 R Undefined Not applicable
6 Reserved, must be written as 0 R Undefined Not applicable
5 Reserved, must be written as 0 R Undefined Not applicable
4 Reserved, must be written as 0 R Undefined Not applicable
3 Reserved, must be written as 0 R Undefined Not applicable
2 CLKOUT enable, 0=disable,
1=enabled
RW 1=enabled Not applicable
1 Reserved, must be written as 0 R Undefined Not applicable
0 Reserved, must be written as 0 R Undefined Not applicable
Bit Description Type Power Up
Condition
Output(s) Affected Notes
7 to 0 Reserved, must be written as 0 R Undefined Not applicable

MK1493-05GLFTR

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution DIFFERENTIAL SPREAD SPECTRUM CLK DRIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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