UJA1065_7 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 25 February 2010 64 of 76
NXP Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Power supply V1; pin V1
t
V1(CLT)
V1 clamped LOW time
during ramp-up of V1
Start-up mode; V1 active 229 - 283 ms
Power supply V2; pin V2
t
V2(CLT)
V2 clamped LOW time
during ramp-up of V2
V2 active 28 - 36 ms
Power supply V3; pin V3
t
w(CS)
cyclic sense period V3C[1:0] = 10; see Figure 14 14 - 18 ms
V3C[1:0] = 11; see Figure 14
28 - 36 ms
t
on(CS)
cyclic sense on-time V3C[1:0] = 10; see Figure 14 345 - 423 μs
V3C[1:0] = 11; see Figure 14
345 - 423 μs
Wake-up input; pin WAKE
t
WU(ipf)
input port filter time V
BAT42
= 5 V to 27 V 5 - 120 μs
V
BAT42
=27V to52V 30 - 250 μs
t
su(CS)
cyclic sense sample setup
time
V3C[1:0] = 11 or 10;
see Figure 14
310 - 390 μs
Watchdog
t
WD(ETP)
earliest watchdog trigger
point
programmed Nominal
Watchdog Period (NWP);
Normal mode
0.45 × NWP - 0.55 × NWP
t
WD(LTP)
latest watchdog trigger point programmed nominal
watchdog period; Normal
mode, Standby mode and
Sleep mode
0.9 × NWP - 1.1 × NWP
t
WD(init)
watchdog initializing period watchdog time-out in Start-up
mode
229 - 283 ms
Fail-safe mode
t
ret
retention time Fail-safe mode; wake-up
detected
1.3 1.5 1.7 s
Reset output; pin RSTN
t
RSTN(CHT)
clamped HIGH time,
pin RSTN
RSTN driven LOW internally
but RSTN pin remains HIGH
115 - 141 ms
t
RSTN(CLT)
clamped LOW time,
pin RSTN
RSTN driven HIGH internally
but RSTN pin remains LOW
229 - 283 ms
t
RSTN(INT)
interrupt monitoring time INTN = 0 229 - 283 ms
t
RSTNL
reset lengthening time after internal or external reset
has been released; RLC = 0
0.9 - 1.1 ms
after internal or external reset
has been released; RLC =1
18 - 22 ms
Table 27. Dynamic characteristics …continued
T
vj
=
40
°
C to +150
°
C; V
BAT42
=5.5V to52V; V
BAT14
=5.5V to27V; V
BAT42
V
BAT14
1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
Symbol Parameter Conditions Min Typ Max Unit
UJA1065_7 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 25 February 2010 65 of 76
NXP Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
[1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient
temperature on wafer level (pretesting). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pretesting
and final testing use correlated test conditions to cover the specified temperature and power supply voltage range.
[2] SPI timing is guaranteed for V
BAT42
voltages down to 5 V. For V
BAT42
voltages down to 4.5 V the guaranteed SPI timing values double,
so at these lower voltages a lower maximum SPI communication speed must be observed.
[3] t
bit
= selected bit time, depends on LSC bit; 50 μs or 96 μs (20 kbit/s or 10.4 kbit/s respectively); bus load conditions (R
1
/R
2
/C
1
):
1kΩ/1 kΩ/10nF; 1kΩ/2 kΩ/6.8 nF; 1 kΩ/open/1 nF; see Figure 27
and Figure 28.
[4]
[5]
Interrupt output; pin INTN
t
INTN
interrupt release after SPI has read out the
Interrupt register
2-- μs
Oscillator
f
osc
oscillator frequency 460.8 512 563.2 kHz
Table 27. Dynamic characteristics …continued
T
vj
=
40
°
C to +150
°
C; V
BAT42
=5.5V to52V; V
BAT14
=5.5V to27V; V
BAT42
V
BAT14
1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
Symbol Parameter Conditions Min Typ Max Unit
δ1 δ3,
t
bus rec()min()
2t
bit
×
-------------------------------
=
δ2 δ4,
t
bus rec()max()
2t
bit
×
--------------------------------
=
Fig 24. SPI timing
001aaa40
5
SCS
SCK
SDI
SDO X
X X
MSB LSB
MSB LSB
t
DOV
floating floating
t
h
t
su
t
SCKL
t
SCKH
t
lead
T
cyc
t
lag
t
SSH
UJA1065_7 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 07 — 25 February 2010 66 of 76
NXP Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Fig 25. Timing test circuit for CAN transceiver
Fig 26. Timing diagram CAN transceiver
10 pF
BAT42 BAT14
GND
CANL
R
C
b
C
CANH
V2
TXDC
RXDC
SBC
001aac30
8
001aac30
9
TXDC
CANH
CANL
V
o(dif)
RXDC
t
t(reces-dom)
t
PHL
HIGH
LOW
HIGH
LOW
dominant
recessive
t
t(dom-reces)
t
PLH

UJA1065TW/5V0/C/T,

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC IC CAN/LIN FAIL-SAFE HS 32
Lifecycle:
New from this manufacturer.
Delivery:
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