100315SC

© 1999 Fairchild Semiconductor Corporation DS010960 www.fairchildsemi.com
September 1991
Revised November 1999
100315 Low Skew Quad Clock Driver
100315
Low Skew Quad Clock Driver
General Description
The 100315 contains four low skew differential drivers,
designed for generation of multiple, minimum skew differ-
ential clocks from a single differential input. This device
also has the capability to select a secondary single-ended
clock source for use in lower frequency system level test-
ing. The 100315 is a 300 Series redesign of the 100115
clock driver.
Features
Low output-to-output skew (50 ps)
Differential inputs and outputs
Secondary clock available for system level testing
2000V ESD protection
Voltage compensated operating range: 4.2V to 5.7V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Pin Descriptions
Note 1: TCLK and CLKSEL are single-ended inputs, with internal 50 k
pull-down resistors.
Connection Diagram
Truth Table
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don't Care
Order Number Package Number Package Descriptions
100315SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Pin Names Description
CLKIN, CLKIN
Differential Clock Inputs
CLK
14
, CLK
14
Differential Clock Outputs
TCLK Test Clock Input (Note 1)
CLKSEL Clock Input Select (Note 1)
CLKSEL CLKIN CLKIN TCLK
CLK
n
CLK
n
LLHXLH
LHLXHL
H X X LLH
HXXHHL
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100315
Absolute Maximum Ratings(Note 2) Recommended Operating
Conditions
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The Recommended Operating Conditions table will define the conditions
for actual device operation.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
DC Electrical Characteristics (Note 4)
V
EE
= 4.2V to 5.7V, V
CC
= V
CCA
= GND, T
C
= 0°C to +85°C
Note 4: The specified limits represent the worst case value for the parameter. Since these worst case values normally occur at the temperature extremes,
additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
AC Electrical Characteristics
V
EE
= 4.2V to 4.8, V
CC
= V
CCA
= GND
Note 5: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (t
OSHL
), or LOW-to-HIGH (t
OSLH
), or in opposite
directions both HL and LH (t
OST
). Parameters t
OST
and t
PS
guaranteed by design.
Storage Temperature 65°C to +150°C
Maximum Junction Temperature (T
J
) +150°C
Case Temperature under Bias (T
C
)0°C to +85°C
V
EE
Pin Potential to Ground Pin 7.0V to +0.5V
Input Voltage (DC) V
CC
to +0.5V
Output Current (DC Output HIGH) 50 mA
Operating Range (Note 2) 5.7V to 4.2V
ESD (Note 3) 2000V
Case Temperature (T
C
)0°C to +85°C
Supply Voltage (V
EE
) 5.7V to 4.2V
Symbol Parameter Min Typ Max Units Conditions
V
OH
Output HIGH Voltage 1025 955 870 mV V
IN
= V
IH(Max)
Loading with
V
OL
Output LOW Voltage 1830 1705 1620 or V
IL(Min)
50 to 2.0V
V
OHC
Output HIGH Voltage 1035 mV V
IN
= V
IH(Min)
Loading with
V
OLC
Output LOW Voltage 1610 or V
IL(Max)
50 to 2.0V
V
IH
Single-Ended Input HIGH Voltage 1165 870 mV Guaranteed HIGH Signal for All Inputs
V
IL
Single-Ended Input LOW Voltage 1830 1475 mV Guaranteed LOW Signal for All Inputs
I
IL
Input LOW Current 0.50 µAV
IN
= V
IL(Min)
I
IH
Input HIGH Current
V
IN
= V
IH(Max)
CLKIN, CLKIN 150 µA
TCLK 250 µA
CLKSEL 250 µA
V
DIFF
Input Voltage Differential 150 mV Required for Full Output Swing
V
CM
Common Mode Voltage V
CC
2V V
CC
0.5V V
I
CBO
Input Leakage Current 10 µAV
IN
= V
EE
I
EE
Power Supply Current 67 35 mA
Symbol Parameter
T
C
= 0°CT
C
= +25°CT
C
= +85°C
Units Conditions
Min Max Min Max Min Max
f
MAX
Maximum Clock Frequency 750 750 750 MHz
t
PLH
Propagation Delay CLKIN,
ns Figures 1, 3
t
PHL
CLKIN to CLK
(14)
, CLK
(14)
Differential 0.59 0.79 0.62 0.82 0.67 0.87
Single-Ended 0.59 0.99 0.62 1.02 0.67 1.07
t
PLH
Propagation Delay, TCLK
0.50 1.20 0.50 1.20 0.50 1.20 ns Figures 1, 2
t
PHL
to CLK
(14)
, CLK
(14)
t
PLH
Propagation Delay, CLKSEL
0.80 1.60 0.80 1.60 0.80 1.60 ns Figures 1, 2
t
PHL
to CLK
(14)
, CLK
(14)
t
TLH
Transition Time
0.30 0.80 0.30 0.80 0.30 0.80 ns Figures 1, 4
t
THL
20% to 80%, 80% to 20%
t
OST
Maximum Skew Opposite Edge
DIFF Output-to-Output Variation 50 50 50 ps (Note 5)
Data to Output Path
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100315
Test Circuit
Note:
Shown for testing CLKIN to CLK1 in the differential mode.
L1, L2, L3 and L4 = equal length 50 impedance lines.
All unused inputs and outputs are loaded with 50 in parallel with 3 pF to GND.
Scope should have 50 input terminator internally.
FIGURE 1. AC Test Circuit
Switching Waveforms
FIGURE 2. Propagation Delay, TCLK, CLKSEL to Outputs
FIGURE 3. Propagation Delay, CLKIN/CLKIN
to Outputs
FIGURE 4. Transition Times

100315SC

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Clock Buffer Quad Clock Driver
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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