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85304AGI-01LFT

P1-P3P4-P6P7-P9P10-P12P13-P15
ICS85304AGI-01 REVISION A FEBRUARY 4, 2013 10 ©2013 Integrated Device Technology, Inc.
ICS85304I-01 Data Sheet LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullup or pulldown resistors; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
Outputs:
LVPECL Outputs
All unused LVPECL output pairs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination
3.3V
V
CC
- 2V
R1
50Ω
R2
50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
+
_
RTT = * Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
LVPECL
Input
R1
84Ω
R2
84Ω
3.3V
R3
125Ω
R4
125Ω
Z
o
= 50Ω
Z
o
= 50Ω
LVPECL Input
3.3V
3.3V
+
_
ICS85304AGI-01 REVISION A FEBRUARY 4, 2013 11 ©2013 Integrated Device Technology, Inc.
ICS85304I-01 Data Sheet LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS85304I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85304I-01 is the sum of the core power plus the power dissipated due to the load.
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to the load.
• Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 55mA = 190.575mW
• Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30mW = 150mW
Total Power_
MAX
(3.465V, with all outputs switching) = 190.575mW + 150mW = 340.575mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a moderate air
flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 91.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.341W * 91.1°C/W = 116.06°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance
JA
for 20 Lead TSSOP, Forced Convection
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 91.1°C/W 86.7°C/W 84.6°C/W
ICS85304AGI-01 REVISION A FEBRUARY 4, 2013 12 ©2013 Integrated Device Technology, Inc.
ICS85304I-01 Data Sheet LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
Figure 5. LVPECL Driver Circuit and Termination
To calculate power dissipation due to the load, use the following equations which assume a 50 load, and a termination voltage of V
CC
– 2V.
• For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.9V
(V
CC_MAX
– V
OH_MAX
) = 0.9V
• For logic low, V
OUT
= V
OL_MAX
= V
CO_MAX
– 1.7V
(V
CC_MAX
– V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OH_MAX
) = [(2V - (V
CC_MAX
– V
OH_MAX
))/R
L
] * (V
CC_MAX
– V
OH_MAX
) =
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OL_MAX
) = [(2V – (V
CC_MAX
– V
OL_MAX
))/R
L]
* (V
CC_MAX
– V
OL_MAX
) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
V
OUT
V
CC
V
CC
- 2V
Q1
RL
50Ω
P1-P3P4-P6P7-P9P10-P12P13-P15

85304AGI-01LFT

Mfr. #:
Buy 85304AGI-01LFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 5 LVPECL OUT BUFFER
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New from this manufacturer.
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