1
®
HI-5701
6-Bit, 30MSPS, Flash A/D Converter
The HI-5701 is a monolithic, 6-bit, CMOS flash Analog-to-
Digital Converter. It is designed for high speed applications
where wide bandwidth and low power consumption are
essential. Its 30MSPS speed is made possible by a parallel
architecture which also eliminates the need for an external
sample and hold circuit. The HI-5701 delivers ±0.7 LSB
differential nonlinearity while consuming only 250mW (Typ)
at 30MSPS. Microprocessor compatible data output latches
are provided which present valid data to the output bus 1.5
clock cycles after the convert command is received. An
overflow bit is provided to allow the series connection of two
converters to achieve 7-bit resolution.
Features
30MSPS with No Missing Codes
Full Power Input Bandwidth . . . . . . . . . . . . . . . . . . 20MHz
No Missing Codes Over Temperature
Sample and Hold Not Required
Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .+5V
Power Dissipation (Max). . . . . . . . . . . . . . . . . . . . .300mW
CMOS/TTL Compatible
•Overflow Bit
Applications
Video Digitizing
Radar Systems
Communication Systems
High Speed Data Acquisition Systems
Pinout
HI-5701
(SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C) PACKAGE
PKG.
DWG. #
HI9P5701K-5 0 to 70 18 Ld SOIC M18.3
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
D4
1
/
2
R
D2
D1
D0 (LSB)
V
DD
V
IN
D3
V
REF
-
D5 (MSB)
OVF
V
SS
NC
CE2
CE1
PHASE
CLK
V
REF
+
Data Sheet September 9, 2005 FN2937.10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Functional Block Diagram
V
IN
V
REF
+
R/2
R
R
R
R
R/2
1
/
2
R
V
REF
-
COMPARATOR
LATCHES
AND
63 TO 6
ENCODER
LOGIC
D
CL
Q
D
CL
Q
D
CL
Q
D
CL
Q
D
CL
Q
D
CL
Q
D
CL
Q
OVERFLOW
(OVF)
D5 (MSB)
D4
D3
D2
D1
D0 (LSB)
CE1
CE2
φ2 (SAMPLE)
φ1 (AUTO BALANCE)
CLOCK
PHASE
V
DD
V
SS
φ2φ1 φ1 φ1 φ2
COMP 64
COMP 63
COMP 32
COMP 2
COMP 1
R
R
HI-5701
3
Absolute Maximum Ratings Thermal Information
Supply Voltage, V
DD
to V
SS
. . . . . . . . . . . (V
SS
- 0.5) < V
DD
< +7V
Analog and Reference Input Pins (V
SS
- 0.5) < V
INA
< (V
DD
+0.5V)
Digital I/O Pins . . . . . . . . . . . . . . . .(V
SS
- 0.5) < V
I/O
< (V
DD
+0.5V)
Operating Conditions
Temperature Range
HI9P5701-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Maximum Power Dissipation at 70
o
C (Note 2) . . . . . . . . . . .635mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range. . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
Electrical Specifications V
DD
= +5.0V; V
REF
+ = +4.0V; V
REF-
= V
SS
= GND; f
S
= Specified Clock Frequency at 50% Duty Cycle;
C
L
= 30pF; Unless Otherwise Specified
PARAMETER TEST CONDITIONS
25
o
C
(NOTE 3)
0
o
C TO 70
o
C
UNITSMIN TYP MAX MIN MAX
SYSTEM PERFORMANCE
Resolution 6--6-Bits
Integral Linearity Error, INL
(Best Fit Line)
f
S
= 20MHz - ±0.5 ±1.25 - ±2.0 LSB
f
S
= 30MHz - ±1.5 - - - LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
f
S
= 20MHz - ±0.3 ±0.6 - ±0.75 LSB
f
S
= 30MHz - ±0.7 - - LSB
Offset Error, V
OS
(Adjustable to Zero)
f
S
= 20MHz (Note 3) - ±0.5 ±2.0 - ±2.5 LSB
f
S
= 30MHz - ±0.5 - - - LSB
Full Scale Error, FSE
(Adjustable to Zero)
f
S
= 20MHz (Note 3) - ±0.25 ±2.0 - ±2.5 LSB
f
S
= 30MHz - ±0.25 - - - LSB
DYNAMIC CHARACTERISTICS
Maximum Conversion Rate No Missing Codes 30 40 - 30 - MSPS
Minimum Conversion Rate No Missing Codes (Note 3) - - 0.125 - 0.125 MSPS
Full Power Input Bandwidth f
S
= 30MHz - 20 - - - MHz
Signal to Noise Ratio, SNR f
S
= 1MHz, f
IN
= 100kHz - 36 - - - dB
f
S
= 30MHz, f
IN
= 4MHz - 31 - - - dB
Signal to Noise Ratio, SINAD f
S
= 1MHz, f
IN
= 100kHz - 35 - - - dB
f
S
= 30MHz, f
IN
= 4MHz - 30 - - - dB
Total Harmonic Distortion f
S
= 1MHz, f
IN
= 100kHz - -44 - - - dBc
f
S
= 30MHz, f
IN
= 4MHz - -38 - - - dBc
Differential Gain f
S
= 14.32MHz, f
IN
= 3.58MHz - 2 - - - %
Differential Phase f
S
= 14.32MHz, f
IN
= 3.58MHz - 2 - - - Degree
ANALOG INPUTS
Analog Input Resistance, R
IN
V
IN
= 4V -30---M
Analog Input Capacitance, C
IN
V
IN
= 0V - 20 - - - pF
RMS Signal
RMS Noise
---------------------------------=
RMS Signal
RMS Noise + Distortion
--------------------------------------------------------------=
HI-5701

HI9P5701K-5

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC ADC 6BIT FLASH 18SOIC W
Lifecycle:
New from this manufacturer.
Delivery:
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