REVISION A 4/14/15
5T9070 DATA SHEET
3 2.5V SINGLE DATA RATE
1:10 CLOCK BUFFER
TERABUFFER™ JR.
PIN DESCRIPTION
Symbol I/O Type Description
A I LVTTL
Clock input
G1 I LVTTL Gate for outputs Q
1 through Q5. When G1 is LOW, these outputs are enabled. When G1 is HIGH, these outputs are asynchro-
nously disabled to the level designated by GL
(1)
.
G2 I LVTTL Gate for outputs Q
6 through Q10. When G2 is LOW, these outputs are enabled. When G2 is HIGH, these outputs are asyn-
chronously disabled to the level designated by GL
(1)
.
GL I LVTTL Specifi es output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW.
Qn O LVTTL
Clock outputs
V
DD PWR Power supply for the device core, inputs, and outputs
GND PWR Power supply return for power
NOTE:
1. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or
be able to tolerate them in down stream circuitry.
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Voltage required to maintain a logic HIGH.
3. Voltage required to maintain a logic LOW.
4. Typical values are at VDD = 2.5V, +25°C ambient.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
(1)
Symbol Parameter Test Conditions Min. Typ.
(4)
Max Unit
I
IH Input HIGH Current VDD = 2.7V VI = VDD/GND — — ±5 μA
I
IL Input LOW Current VDD = 2.7V VI = GND/VDD — — ±5
V
IK Clamp Diode Voltage VDD = 2.3V, IIN = -18mA — - 0.7 - 1.2 V
V
IN DC Input Voltage - 0.3 +3.6 V
V
IH DC Input HIGH
(2)
1.7 — V
V
IL DC Input LOW
(3)
— 0.7 V
V
OH Output HIGH Voltage IOH = -12mA VDD - 0.4 — V
I
OH = -100μA VDD - 0.1 — V
V
OL Output LOW Voltage IOL = 12mA — 0.4 V
I
OL = 100μA — 0.1 V
