ADP5587 Data Sheet
Rev. D | Page 8 of 24
THEORY OF OPERATION
CONTROL
REGISTERS
CONTROL
INTERFACE
R7
R6
R5
R4
R3
R2
R1
R0
C0
C1
C2
C3
C4
C5
C6
C7
C9
C8
A0A1
A2A3
A4
A5A6
A7
B0B1B2B3B4B5B6B7
C0C1C2C3C4C5C6C7
D0D1D2D3D4D5D6D7
E0E1E2E3E4E5E6E7
F0F1F2F3F4F5F6F7
G0G1G2G3G4G5G6G7
H0H1H2H3H4H5H6H7
I0I1I2I3I4I5I6I7
J0J1J2J3J4J5J6J7
SCL
SDA
RST
INT
V
CC
GND
V
CC
SCL
SDA
19
21
23
22
18
17
20
24
1
2 3
4
5 6
7 8
9
10 11 12 13 14 15 16
ADP5587
RST
INT
08612-005
Figure 9. Typical Operating Circuit
The ADP5587 is a GPIO expander that can be configured either
as an 18 I/O port expander or as a 10 column × 8 row keypad
matrix (80 keys maximum). It is ideal for cellular phone designs
and other portable devices that require a large extended keypad
and/or expanded I/Os. When smaller size keypads are required,
unused GPIOs in the keypad matrix can be used as I/Os (GPOs
and GPIs). All GPIOs (rows and columns) default to GPIs at
power-up with pull-ups and debounce enabled.
KEYPAD OPERATION
Any number of rows and columns, up to 10 columns × 8 rows,
can be configured to be part of the keypad matrix. The rows and
columns that make up the keypad matrix must be configured by
setting the corresponding bits in Register 0x1D to Register 0x1F.
Key presses and releases appear in the key event table/registers
with a decimal value of 1 (0x01 hexadecimal or 0000001 binary)
through a decimal value of 80 (0x50 hexadecimal or 1010000
binary). See Table 9 for key event number assignments. The
keypad, in idle mode, is configured with columns driven low
and rows as inputs configured high with pull-up resistors.
Table 9. Key Event Number Assignment Table
Row C0 C1 C2 C3 C4 C5 C6 C7 C8 C9
R0
1 2 3 4 5 6 7 8 9 10
R1
11 12 13 14 15 16 17 18 19 20
R2
21 22 23 24 25 26 27 28 29 30
R3
31 32 33 34 35 36 37 38 39 40
R4
41 42 43 44 45 46 47 48 49 50
R5
51 52 53 54 55 56 57 58 59 60
R6
61 62 63 64 65 66 67 68 69 70
R7
71 72 73 74 75 76 77 78 79 80
When one key press or multiple key presses (short between
column and row) occur, the internal state machine checks the
row pins to determine which one is driven low and then triggers
an internal interrupt. The state machine then starts a key scan
cycle to determine which columns are involved in the key press.
After a key has been pressed for 25 ms, the state machine sets
the appropriate key number in the key event status register with
the key-pressed bits set (the MSB in the key event register) in
the order detected. The state machine then sets the KE_INT bit
in Register 0x02. If the KE_IEN field in Register 0x01 is set, an
interrupt is sent to the host processor.
