4
ICS9248-195
0375E—12/15/08
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched register values will be inverted from pin values. Default latch condition is for all latched inputs to
be floating (pulled up via internal resistor) at power-up.
Byte 2: Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB71 )siD/nE(F_KLCICP
6tiB811 )siD/nE(6KLCICP
5tiB711 )siD/nE(5KLCICP
4tiB311 )siD/nE(4KLCICP
3tiB211 )si
D/nE(3KLCICP
2tiB111 )siD/nE(2KLCICP
1tiB011 )siD/nE(1KLCICP
0tiB81 )siD/nE(0KLCICP
Byte 1: Active/Inactive Register (1 = enable, 0 = disable)
Byte 3: Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB641 )siD/nE(F_KLCUPC
5tiB-0 )devreseR(
4tiB-0 )devreseR(
3tiB931 )siD/nE(F_MARDS
2tiB241 )
siD/nE(2KLCUPC
1tiB341 )siD/nE(1KLCUPC
0tiB541 )siD/nE(0KLCUPC
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-0 )devreseR(
5tiB-0 )devreseR(
4tiB-0 )devreseR(
3tiB821 )siD/nE(7MARDS
2tiB921 )siD/nE(6
MARDS
1tiB131 )siD/nE(5MARDS
0tiB231 )siD/nE(4MARDS
5
ICS9248-195
0375E—12/15/08
Byte 4: Active/Inactive Register (1 = enable, 0 = disable)
Byte 5: Active/Inactive Register (1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched register values will be inverted from pin values. Default latch condition is for all latched inputs to be floating
(pulled up via internal resistor) at power-up.
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-0 )devreseR(
5tiB-0 #)84_42LES(
4tiB-0 #0SFdehctaL
3tiB-0 #1SFdehctaL
2tiB-0 #2SFdehctaL
1
tiB-0 #3SFdehctaL
0tiB-1 )devreseR(
tiB#niPDWPnoitpircseD
7tiB431 )siD/nE(3MARDS
6tiB531 )siD/nE(2MARDS
5tiB731 )siD/nE(1MARDS
4tiB831 )siD/nE(0MARDS
3tiB621 )siD/nE
(zHM84
2tiB521 )siD/nE(zHM42
1tiB841 )siD/nE(1FER
0tiB21 )siD/nE(0FER
6
ICS9248-195
0375E—12/15/08
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= V
DDL
= 3.3 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage V
IH
2V
DD
+ 0.3 V
Input Low Voltage V
IL
V
SS
- 0.3 0.8 V
C
L
= 0 pF; Select @ 66MHz 150
C
L
= 0 pF; Select @ 100MHz 170
C
L
= 0 pF; Select @ 133MHz 180
Powerdown Current
I
DDPD
CL = 0 pF; Input address VDD or GND 600
µA
Input Frequency F
i
V
D
D
= 3.3 V 14.32 MHz
Input Capacitance
1
C
IN
Logic Inputs 5 pF
C
INX
X1 & X2 pins 27 45 pF
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target Freq. 5.5 ms
Skew
1
t
CPU-PCI1
V
T
= 1.5 V
14ns
1
Guaranteed by design, not 100% tested in production.
mA
Operating Supply
Current
I
DD3.3OP
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
C
L
= 0 pF; Select @ 66.8 MHz 15
C
L
= 0 pF; Select @ 100 MHz 18
C
L
= 0 pF; Select @ 133 MHz 25
Powerdown Current
I
DDLP
D
CL = 0 pF; Input address VDD or GND
10
mA
Skew
1
t
CPU-PCI 2
V
T
= 1.5 V; V
TL
= 1.25 V
14ns
1
Guaranteed by design, not 100% tested in production.
I
DDL2.5
O
perating SupplyCurren
t
mA

ICS9248BF-195

Mfr. #:
Manufacturer:
Description:
IC FREQ GENERATOR/BUFFER 48-SSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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