9397 750 12667 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 01 — 29 June 2004 8 of 21
Philips Semiconductors
SAF7167AHW
YUV-to-RGB digital-to-analog converter
Since only one control register KD[7:0] provides the data value for pixel data comparison,
when at 2 × 8-bit or 3 × 8-bit pixel input modes, it is presumed that all input bytes (lower,
middle or higher) of each pixel must be the same as KD[7:0] in order to make graphics
colour key active.
The polarity of EXTKEY can be selected with KINV. With KINV = 0, EXTKEY = HIGH
switches analog mixers to select DAC outputs. Before the internal keying signal switches
the analog multiplexers, it can be further delayed up to 7 PCLK cycles with the control bits
KDLY[2:0].
7.3 Voltage output amplifiers
Before the analog input enters the analog mixers, it passes through voltage output
amplifiers. Level shifters are used internally to provide an offset of 0.2 V and an amplifier
gain of 2 for analog inputs to match with the output levels from DACs. After buffering with
voltage output amplifiers, the final RGB outputs can drive a 150 Ω load directly (25 Ω
internal resistor, 47 Ω external serial resistor, and 75 Ω load resistor) at the monitor side
(see Figure 9).
The output voltage level of DAC ranges from the lowest level 0.2 V (zero code) to the
highest level 1.82 V (all one code).
With the digital input YUV video data in accordance with ITU-R BT.601, the RGB output of
8-bit DAC actually ranges from the 16th step (black) to the 235th step (white). Therefore,
after the voltage divider with external serial resistor and monitor load resistor, the output
voltage range to a monitor is approximately 0.7 V (p-p).
7.4 I
2
C-bus control
Only one control byte is needed for the SAF7167AHW. The I
2
C-bus format is shown in
Table 9.
[1] S = START condition.
[2] SLAVE ADDRESS = 1011 111X; X = R/W control bit. X = 0: order to write. X = 1: order to read (not used for
SAF7167AHW).
[3] A = acknowledge; generated by the slave.
[4] SUBADDRESS = subaddress byte.
[5] DATA = data byte.
[6] P = STOP condition.
Table 8: KMOD[2:0]
KMOD[2:0] Pixel type Remark
100 8-bit pixel pseudo colour mode
101 2 × 8-bit pixel high colour mode 1 with pixels
given at both rising and falling
edges of PCLK
110 2 × 8-bit pixel high colour mode 2 with pixels
given only at rising edges of
PCLK
111 3 × 8-bit pixel true colour mode
Table 9: I
2
C-bus format
S
[1]
SLAVE ADDRESS
[2]
A
[3]
SUBADDRESS
[4]
A
[3]
DATA
[5]
A
[3]
P
[6]
