Low Power Mixer/Limiter/RSSI
3 V Receiver IF Subsystem
AD608
Rev. C
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FEATURES
Mixer
−15 dBm, 1 dB compression point
−5 dBm IP3
24 dB conversion gain
>500 MHz input bandwidth
Logarithmic/limiting amplifier
80 dB RSSI range
±3° phase stability over 80 dB range
Low power
21 mW at 3 V power consumption
CMOS-compatible power-down to 300 μW typical
200 ns enable/disable time
APPLICATIONS
PHS, GSM, TDMA, FM, or PM receivers
Battery-powered instrumentation
Base station RSSI measurements
GENERAL DESCRIPTION
The AD608 provides a low power, low distortion, low noise mixer
as well as a complete, monolithic logarithmic/limiting amplifier
that uses a successive-detection technique. In addition, the AD608
provides both a high speed received signal strength indicator
(RSSI) output with 80 dB dynamic range and a hard-limited
output. The RSSI output is from a two-pole postdemodulation
low-pass filter and provides a loadable output voltage of 0.2 V to
1.8 V. The AD608 operates from a single 2.7 V to 5.5 V supply
at a typical power level of 21 mW at 3 V.
The RF and local oscillator (LO) bandwidths both exceed
500 MHz. In a typical IF application, the AD608 can accept the
output of a 240 MHz surface acoustic wave (SAW) filter and down-
convert it to a nominal 10.7 MHz IF with a conversion gain of
24 dB (Z
IF
= 165 Ω). The AD608 logarithmic/limiting amplifier
section handles any IF from low frequency (LF) up to 30 MHz.
The mixer is a doubly balanced gilbert-cell mixer and operates
linearly for RF inputs spanning −95 dBm to −15 dBm. It has a
nominal −5 dBm third-order intercept. An on-board LO pre-
amplifier requires only −16 dBm of LO drive. The current output
of the mixer drives a reverse-terminated, industry-standard
10.7 MHz, 330 Ω filter.
The nominal logarithmic scaling is such that the output is +0.2 V
for a sinusoidal input to the IF amplifier of −75 dBm and +1.8 V
at an input of +5 dBm; over this range, the logarithmic confor-
mance is typically ±1 dB. The logarithmic slope is proportional
to the supply voltage. A feedback loop automatically nulls the
input offset of the first stage down to the submicrovolt level.
The AD608 limiter output provides a hard-limited signal output
at 400 mV p-p. The voltage gain of the limiting amplifier to this
output is more than 100 dB. Transition times are 11 ns and the
phase is stable to within ±3° at 10.7 MHz for signals from −75 dBm
to +5 dBm.
The AD608 is enabled by a CMOS logic-level voltage input,
with a response time of 200 ns. When disabled, the standby
power is reduced to 300 μW within 400 ns.
The AD608 is specified for the industrial temperature range of
−25°C to +85°C for 2.7 V to 5.5 V supplies and −40°C to +85°C for
3.0 V to 5.5 V supplies. This device comes in a 16-lead plastic SOIC.
FUNCTIONAL BLOCK DIAGRAM
24dB MIXER GAIN
110dB LIMITER GAIN
90dB RSSI
BIAS
MXOP
MIXER
BPF
DRIVER
VMID
LO
PREAMP
AD608
RFHI
RFLO
IF INPUT
–75dBm TO
+15dBm
2
IFHI
IFLO
LMOP
VPS2
RSSI
FDBK
COM3
FINAL
LIMITER
100nF
10nF
330Ω
±50µA
330Ω
MIDSUPPLY
IF BIAS
LIMITER
OUTPUT
400mV p-p
PRUP
RF INPUT
–95dBm TO
–15dBm
1
VPS1 COM1 COM2LOHI
RSSI OUTPUT
20mV/dB
0.2V TO 1.8V
3dB NOMINAL
INSERTION LOSS
+2.7V TO 5.5V
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
7 FULL-WAVE
RECTIFIER CELLS
2.7V TO
5.5V
LO INPUT
–16dBm
CMOS LOGIC
INPUT
±6mA MAX OUTPUT
(±890mV INTO 165Ω)
100Ω
18nF
1
–15dBm = ±56mV MAXIMUM FOR LINEAR OPERATION.
2
39.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY.
2MHz
LPF
10.7MHz
BAND-PASS
FILTER
5
6
1 2 3 4 16
8
7
10
13
9
15
14
12
11
+
+
+
07886-001
Figure 1.
