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NB6L11DG

P1-P3P4-P6P7-P9P10-P12P13-P13
© Semiconductor Components Industries, LLC, 2013
June, 2013 − Rev. 9
1 Publication Order Number:
NB6L11/D
NB6L11
2.5 V/3.3 V Multilevel Input to
Differential LVPECL/LVNECL
1:2 Clock or Data
Fanout Buffer/Translator
The NB6L11 is an enhanced differential 1:2 clock or data fanout
buffer/translator. The device has the same pinout and is functionally
equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the
device is optimized for the systems that require LOW skew, LOW
jitter and LOW power consumption.
Differential input can be configured to accept single−ended signal
by applying an external reference voltage to unused complementary
input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS,
CML, or LVDS. The outputs are 800 mV ECL signals.
Features
• Input Clock Frequency w 6 GHz
• Input Data Rate w 6 Gb/s
• Low 14 mA Typical Power Supply Current
• 150 ps Typical Propagation Delay
• 5 ps Typical Within Device Skew
• 75 ps Typical Rise/Fall Times
• PECL Mode Operating Range:
V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
• NECL Mode Op rating Range:
V
CC
= 0 V with V
EE
= −2.375 V to −3.465 V
• Open Input Default State
• Q Outputs Will Default LOW with Inputs Open or at V
EE
• LVDS, LVPECL, LVNECL, LCMOS, LVTTL and CML Input
Compatible
• These Devices are Pb−Free and are RoHS Compliant
6L11
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
SO−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
TSSOP−8
DT SUFFIX
CASE 948R
6L11
ALYW G
G
1
8
1
8
1
8
1
8
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
NB6L11
http://onsemi.com
2
1
2
3
4
5
6
7
8
D
V
EE
V
CC
Figure 1. Pinout (Top View) and Logic Diagram
Q0
D
Q1
Q1
Q0
R
2
R
2
R
1
R
1
Table 1. PIN DESCRIPTION
Pin Name I/O Default State Description
1 Q0 ECL Output − Non−inverted differential clock/data output 0. Typically termin-
ated with 50 W Resistor to V
TT
= V
CC
− 2 V.
2 Q0 ECL Output − Inverted differential clock/data output 0. Typically terminated with
50 W resistor to V
TT
= V
CC
− 2 V.
3 Q1 ECL Output − Non−inverted differential clock/data output 1. Typically termin-
ated with 50 W resistor to V
TT
= V
CC
− 2 V.
4 Q1 ECL Output − Inverted differential clock/data output 1. Typically terminated with
50 W resistor to V
TT
= V
CC
− 2 V.
5 V
EE
− − Negative power supply voltage
6 D LVDS, CML, LVPECL, LVNECL,
LVCMOS, LVTTL Input
HIGH
Inverted differential clock/data input. Internal 37.5 kW to V
CC
and
75 kW to V
EE
.
7 D LVDS, CML, LVPECL, LVNECL,
LVCMOS, LVTTL Input
LOW
Non−inverted differential clock/data input. Internal 75 kW to V
CC
and 37.5 kW to V
EE
.
8 V
CC
− − Positive power supply voltage
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Resistor R1
37.5 kW
Internal Input Resistor R2
75 kW
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 1 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg
SOIC−8
TSSOP−8
Level 1
Level 1
Level 1
Level 3
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 167 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
NB6L11
http://onsemi.com
3
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply V
EE
= 0 V 3.6 V
V
EE
Negative Power Supply V
CC
= 0 V −3.6 V
V
I
Positive Input Voltage
Negative Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
v V
CC
V
I
w V
EE
3.6
−3.6
V
V
V
INPP
Differential Input Voltage |D − D| V
CC
− V
EE
w 2.8 V
V
CC
− V
EE
t 2.8 V
2.8
|V
CC
− V
EE
|
V
I
out
Output Current Continuous
Surge
25
50
mA
mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W
T
sol
Wave Solder Standard
Pb−Free
v 3 sec @ 248°C
v 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
P1-P3P4-P6P7-P9P10-P12P13-P13

NB6L11DG

Mfr. #:
Buy NB6L11DG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 2.5V/3.3V Multilevel 1:2 Clock / Fanout
Lifecycle:
New from this manufacturer.
Delivery:
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