9
FN6828.3
December 9, 2015
Block Diagram
Theory of Operation
The ISL9103, ISL9103A is a step-down switching regulator
optimized for battery-powered handheld applications. The
regulator operates at typical 2.4MHz fixed switching
frequency under heavy load condition to allow small external
inductor and capacitors to be used for minimal printed-circuit
board (PCB) area. At light load, the regulator can
automatically enter the skip mode (PFM mode) to reduce the
switching frequency to minimize the switching loss and to
maximize the battery life. The quiescent current under skip
mode, and under no load and no switch condition is typically
only 20µA. The supply current is typically only 0.05µA when
the regulator is disabled.
PWM Control Scheme
The ISL9103, ISL9103A uses the peak-current-mode
pulse-width modulation (PWM) control scheme for fast
transient response and pulse-by-pulse current limiting.
Figure 22 shows the circuit functional block diagram. The
current loop consists of the oscillator, the PWM comparator
COMP, current sensing circuit, and the slope compensation
for the current loop stability. The current sensing circuit
consists of the resistance of the P-Channel MOSFET when it
is turned on and the Current Sense Amplifier (CSA). The
control reference for the current loops comes from the Error
Amplifier (EAMP) of the voltage loop.
The PWM operation is initialized by the clock from the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the P-Channel
MOSFET starts ramping up. When the sum of the CSA
output and the compensation slope reaches the control
reference of the current loop, the PWM comparator COMP
sends a signal to the PWM logic to turn off the P-Channel
MOSFET and to turn on the N-Channel MOSFET. The
N-MOSFET remains on till the end of the PWM cycle. Figure 23
shows the typical operating waveforms during the normal PWM
operation. The dotted lines illustrate the sum of the slope
compensation ramp and the CSA output.
SW
+
CSA
+
+
OCP
VREF1
SKIP
+
+
X
SLOPE
COMP
SO
FT
STA
RT
SOFT-
START
VREF
EAMP
COMP
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
DRIVER
FB
SHUTDOWN
VIN
GND
OSCILLATOR
ZERO-CROSS
SENSING
BLEEDING
FET
*NO TE
BANDGAP
SCP
+
EN
SHUTDOWN
100
VREF2
VREF3
*NOTE: FOR FIXED OUTPUT OPTIONS ONLY
FIGURE 22. FUNCTIONAL BLOCK DIAGRAM
NOTE: For Adjustable output version, the internal feedback resistor divider is disabled and the FB pin
is directly connected to the error amplifier.
ISL9103, ISL9103A
