NBVSPA017LNHTAG Datasheet NBVSPA019LNHTAG, NBVSPA018LNHTAG, NBVSPA027LNHTAG | P1-P3

December, 2010 − Rev. 1

1 Publication Order Number:

NBVSPA015/D

NBVSPA015 Series

3.3 V, LVDS

Voltage-Controlled Clock

Oscillator (VCXO)

PureEdget Product Series

The NBVSPXXXX voltage−controlled crystal oscillator (VCXO)

devices are designed to meet today’s requirements for 3.3 V LVDS

clock generation applications. These devices use a high Q

fundamental mode crystal and Phase Locked Loop (PLL) multiplier to

provide a wide range of frequencies from 60 MHz to 700 MHz

(factory configurable per user specifications) with a pullable range of

±100 ppm and a frequency stability of ±50 ppm. The silicon−based

PureEdget products design provides users with exceptional

frequency stability and reliability. They produce an ultra low jitter and

phase noise LVDS differential output.

The NBVSPXXXX series devices are a member of ON

Semiconductor’s PureEdget clock family that provides accurate and

precision clock generation solutions.

Available in the industry standard 5.0 x 7.0 x 1.8 mm and in a new

smaller 3.2 x 5.0 x 1.2 mm SMD (CLCC) package on 16 mm tape and

reel in quantities of 1,000.

Features

• LVDS Differential Output

• Uses High Q Fundamental Mode Crystal

• Ultra Low Jitter and Phase Noise − 0.5 ps (12 kHz − 20 MHz)

• Factory Configurable Frequencies from 60 MHz to 700 MHz (see

Standard Frequencies in the Ordering Information Table on page 6)

• Pullable Range Minimum of ±100 ppm

• Frequency Stability of ±50 ppm

• Control Voltage with Positive Slope

• Voltage Control Linearity of ±10%

• Hermetically Sealed Ceramic SMD Packages of size 5.0 x 7.0 x

1.8 mm and 3.2 x 5.0 x 1.2 mm

• Operating Range: 3.3 V ±10%

• These Devices are Pb−Free and are RoHS Compliant

Applications

• Networking

• SONET

• 10 Gigabit Ethernet

• Networking Base Stations

• Broadcasting

http://onsemi.com

MARKING DIAGRAMS

NBVSPXXXX = NBVSPXXXX (±50 ppm)

XXX.XXXX = Output Frequency (MHz)

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

6 PIN CLCC

LN SUFFIX

CASE 848AB

NBVSPXXXX

XXX.XXXX

AWLYYWWG

6 PIN CLCC

LU SUFFIX

CASE 848AC

NBVSPXXXX

XXX.XXXX

AWLYYWWG

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

NBVSPA015 Series

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Figure 1. Simplified Logic Diagram

PLL

Clock

Multiplier

Crystal

GNDOEV

CLK CLKV

654

123

LVDS

20−30

MHz

GND

CLK

Figure 2. Pin Connections (Top View)

Table 1. PIN DESCRIPTION

Pin No. Symbol I/O Description

1 V

(Note 1) Analog Input Analog control voltage input pin that adjusts output oscillation frequency. f

= 1.65 V

2 OE LVTTL/LVCMOS

Control Input

Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.

See OE pin description Table 2.

3 GND Power Supply Ground at 0 V. Electrical and Case Ground.

4 CLK LVDS Output

Non−Inverted Clock Output. Typically loaded with 100 W receiver termination resistor

across differential pair.

5 CLK LVDS Output

Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across

differential pair.

6 V

Power Supply Positive Power Supply Voltage. Voltage should not exceed 3.3 V ±10%.

1. Control voltage has a positive slope with a typical linearity of ±10%; V

= 1.65 V ± 1 V.

Table 2. OUTPUT ENABLE TRI−STATE FUNCTION

OE Pin Output Pins

Open Active

HIGH Level Active

LOW Level High Z

Table 3. ATTRIBUTES

Characteristic Value

Input Default State Resistor

170 kW

ESD Protection Human Body Model

Machine Model

2 kV

200 V

Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test

2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.

NBVSPA015 Series

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Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Units

Positive Power Supply GND = 0 V 4.6 V

Control Input (V

and OE) V

≤ V

+ 200 mV

≥ GND − 200 mV

OSC

Output Short Circuit Current CLK to CLK

CLK or CLK to GND

Continuous

Operating Temperature Range −40 to +85 °C

stg

Storage Temperature Range −55 to +120 °C

sol

Wave Solder See Figure 4 260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

Table 5. DC CHARACTERISTICS (V

= 3.3 V ±10%, GND = 0 V, T

= −40°C to +85°C) (Note 3)

Symbol

Characteristic Conditions Min. Typ. Max. Units

Power Supply Current 75 100 mA

OE and FSEL Input HIGH Voltage 2000 V

OE and FSEL Input LOW Voltage GND − 300 800 mV

Input HIGH Current OE −100 +100

Input LOW Current OE −100 +100

Change in Magnitude of V

for

Complementary Output States

(Note 4) 0 1 25 mV

Offset Voltage 1125 1375 mV

Change in Magnitude of V

for

Complementary Output States

(Note 4) 0 1 25 mV

Output HIGH Voltage 1425 1600 mV

Output LOW Voltage 900 1075 mV

Differential Output Voltage 250 450 mV

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

3. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 3.

4. Parameter guaranteed by design verification not tested in production.

P1-P3 P4-P6 P7-P8

NBVSPA017LNHTAG

Mfr. #:

Buy NBVSPA017LNHTAG

Manufacturer:

ON Semiconductor

Description:

IC OSC VCXO 156.25MHZ 6CLCC

Lifecycle:

New from this manufacturer.

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NBVSPA017LNHTAG

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