ICS854104AGI REVISION B JANUARY 30, 2014 2 ©2014 Integrated Device Technology, Inc.
ICS854104I DATA SHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Table
Table 3. Output Enable Function Table
Number Name Type Description
1 OE0 Input Pullup
Output enable pin for Q0, nQ0 outputs. See Table 3. LVCMOS/LVTTL
interface levels.
2 OE1 Input Pullup
Output enable pin for Q1, nQ1 outputs. See Table 3. LVCMOS/LVTTL
interface levels.
3 OE2 Input Pullup
Output enable pin for Q2, nQ2 outputs. See Table 3. LVCMOS/LVTTL
interface levels.
4V
DD
Power Positive supply pin.
5 GND Power Power supply ground.
6 CLK Input Pulldown Non-inverting differential clock input.
7 nCLK Input Pullup/Pulldown Inverting differential clock input. V
DD
/2 default when left floating.
8 OE3 Input Pullup
Output enable pin for Q3, nQ3 outputs. See Table 3. LVCMOS/LVTTL
interface levels.
9, 10 nQ3, Q3 Output Differential output pair. LVDS interface levels.
11, 12 nQ2, Q2 Output Differential output pair. LVDS interface levels.
13, 14 nQ1, Q1 Output Differential output pair. LVDS interface levels.
15, 16 nQ0, Q0 Output Differential output pair. LVDS interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
Inputs Outputs
OE[3:0] Q[0:3], nQ[0:3]
0 High-Impedance
1 Active (default)