CS2082EDWR20

CS2082
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7
Each SHx pin is pulled up to V
BAT
while each SLx pin is
pulled down to GND through separate nominal 10 k
resistors, thus biasing each normal fire path to about 1/2
V
BAT
. An open fire path has been detected if both the SBx
and SGx bits are set for that path. To detect faults between
fire paths and to test driver function, each driver should be
activated individually. The activated driver should cause its
respective fault bit to be set. If an activated driver does not
set its respective fault bit, a driver fault has been detected. If
an activated driver causes the fault bit of an inactivated
driver to be set, a fault between fire paths has been detected.
Table 4 defines the implied ranges over which the various
types of faults can be detected.
Table 4. Implied Resistive Fault Detection Ranges
Fault Min Nom Max Unit
Short to Ground 1 5 10 k
Short to Battery 1 5 10 k
Open 5 20 40 k
Driver Open 1 5 10 k
Driver Shorted 1 5 10 k
Squib to Squib 1 5 10 k
Squib Resistance Measurement – $3d
The $3d command activates squib resistance
measurement for the selected firing path. The respective
active–high bit definitions are shown in Table 5. At
power–up, the default path is ‘None.’
Table 5. Squib Resistance Path Select
D3 D2 D1 D0 Path
x x 0 0 NONE
x x 0 1 SQUIB 1
x x 1 0 SQUIB 2
x x 1 1 NONE
Squib resistance is measured by forcing 50 mV nominal
(proportional to V
CC
) across the squib. The resulting squib
current is passed to an external load resistor at the MR pin,
converting the current back into a voltage. This voltage may
be read directly at the MR pin, or passed through the analog
multiplexer to be read at the A
OUT
pin. The known values of
the squib differential voltage (V
DIFF
) and the MR resistance
(R
MR
), and the measured MR voltage (V
MR
) indicate squib
resistance such that:
R
SQUIB
R
MR
V
DIFF
V
MR
Typical MR voltage response for R
MR
= 50 over a squib
resistance range of 0.6 to 6.0 is illustrated in Figure 2.
Figure 2. Typical MR Voltage Response
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.6 1.4 2.2 3.0 3.8 4.6 5.4
R
SQUIB
V
MR
Measurement accuracy of the CS2082 with combined
tolerances and with and external 1% load resistor at the MR
pin can be defined by the equation:
R
SQ(E)
V
DIFF(IDEAL)
R
MR(IDEAL)
V
DIFF
12%
R
SQ(A)
1% R
MR
1%
R
SQ(A)
12.5%15.94%
where V
DIFF(IDEAL)
and R
MR(IDEAL)
are the assumed
values for the squib resistance solution algorithm, R
SQ(A)
is
the actual squib resistance, and R
SQ(E)
is the result of the
solution algorithm. An additional error may be added if the
MR voltage is measured through the analog multiplexer.
In operation, current is sourced from V
BAT
to the SHx pin,
through the squib to the SLx pin, and returned to ground
through the MR load resistor. Current clamps are provided
for both the SHx and SLx pins and a voltage clamp is
provided for the MR pin. These clamps along with the
resolution of the ADC are the constraining factors for the
minimum and maximum measurable squib resistance
values.
The minimum measurable squib resistance can be defined
as:
V
DIFF(MIN)
I
LIM(MAX)
R
SQUIB(MIN)
V
DIFF(MIN)
R
MR(MIN)
V
CLAMP(MAX)
The maximum measurable squib resistance can be
defined as:
R
SQUIB(MAX)
V
DIFF(MAX)
R
MR(MAX)
(2
n
1)
V
CC(MIN)
In the above equations, V
DIFF
is the SHx–SLx forced
differential voltage, I
LIM
is the SHx resistive measure
current limit, V
CLAMP
is the MR clamp voltage, R
MR
is the
toleranced MR load resistor value and n is the number of bits
of resolution of the ADC.
It should be noted that during resistive measurements,
faults to GND or BAT (dependent on V
BAT
voltage and
CS2082
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8
squib resistance) may be reported by the fault register and
should be ignored.
Power Dissipation during resistive measurement can be
calculated as:
P I
SQUIB
(V
BAT
V
DIFF
) (I
SQUIB
R
MR)
where V
BAT
is the voltage at the CS2082 V
BAT
pin and
I
SQUIB
is the measurement current through the squib. A
typical value for P is 300 mW when V
BAT
= 13.5,
V
DIFF
= 50 mV, R
SQUIB
= 2.0 and R
MR
= 49.9 .
The resultant increase in power dissipation will cause a
corresponding increase in die temperature which will cause
a corresponding decrease in time to thermal shutdown of the
CS2082. To minimize the impact of squib resistive
measurements on time to thermal shutdown a 5% duty cycle
is recommended.
Analog MUX – $4d
The $4d command selects one of five states at the A
OUT
pin. The states are: High–Z; MR voltage; A
IN
voltage;
proportion of V
BAT
; proportion of V
RES
. The active–high
Analog Mux select register bit definitions are shown in
Table 6. All other states will be interpreted as High–Z. At
power–up, the default state is ‘High–Z.’
Table 6. Analog MUX Output Select
D3 D2 D1 D0 State
0 0 0 0 High–Z
0 0 0 1 MR
0 0 1 0 AIN
0 1 0 0 BAT
1 0 0 0 RES
Low Side Switch Control – $5d
The $5d command activates the low side switches. When
a data bit is low that switch is turned on. More than one
switch can be activated at a time. Bit assignment is shown in
Table 7. At power–up, no switches are active.
Table 7. Low Side Switch Select
D3 D2 D1 D0 Active
x x 0 0 BOTH
x x 0 1 SL2
x x 1 0 SL1
x x 1 1 NONE
Auxiliary Control Register – $6d
The $6d command selects the V
RES
Monitoring trip
threshold. The threshold determines when the $1x Status
Register reports V
RES
= 1. Bit assignment is shown in Table
8. At power–up, default trip is 17 V.
Table 8. V
RES
Monitor Trip Select
D3 D2 D1 D0 Trip
x x x 0 17 V
x x x 1 23 V
High Side Switch Control – $Ad
The $Ad command activates the high side switches. When
a data bit is high, that switch is turned on. More than one
switch can be activated at a time. Bit assignment is shown in
Table 9. Note that the $5d and $Ad commands are binary
complements, i.e., by sending 1010xx11, both high side
switches are activated, and by sending the complement
0101xx00, both low side switches are activated. At
power–up, no switches are active.
Table 9. High Side Switch Select
D3 D2 D1 D0 Active
x x 0 0 NONE
x x 0 1 SH1
x x 1 0 SH2
x x 1 1 BOTH
CS2082
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9
GND
V
CC
D
IN
VR2
SH2
SL2
FG2
A
IN
A
OUT
CS
V
BAT
CHRG
V
RES
VR1
SH1
SL1
FG1
D
OUT
CLK
MR
CS2082
C
CM
C
CM
C
CM
C
CM
C
DM
C
DM
+ +
C
RES
C
RES
MCU
C
MR
V
IGN
V
CC
V
BOOST
Analog
Input
Figure 3. Application Diagram

CS2082EDWR20

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC DL AIRBAG DEPLOY ASIC 20SOIC
Lifecycle:
New from this manufacturer.
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