CSP2510CPG

4
0ºC TO 85ºC TEMPERATURE RANGE
IDTCSP2510C
3.3V PHASE-LOCK LOOP CLOCK DRIVER
DC ELECTRICAL CHARACTERISTICS OVER OPERATING FREE-AIR TEMPERA-
TURE RANGE
(1)
Symbol Description Test Conditions VDD Min. Typ.
(2)
Max. Unit
VIK Input Clamp Voltage II = -18mA 3V ⎯⎯– 1.2 V
VIH Input HIGH Level 2 ⎯⎯ V
VIL Input LOW Level ⎯⎯0.8 V
I
OH = -100μA Min. to Max. VDD – 0.2 ⎯⎯
V
OH HIGH Level Output Voltage IOH = -12mA 3V 2.1 ⎯⎯ V
IOH = -6mA 3V 2.4 ⎯⎯
IOL = 100μA Min. to Max. ⎯⎯0.2
VOL LOW Level Output Voltage IOL = 12mA 3V ⎯⎯0.8 V
IOL = 6mA 3V ⎯⎯0.55
II Input Current VI = VDD or GND 3.6V ⎯⎯±5 μA
IDD Supply Current VI = VDD or GND, AVDD = GND, 3.6V ⎯⎯10 μA
IO = 0, Outputs: LOW or HIGH
ΔIDD Change in Supply Current One input at VDD - 0.6V, other inputs at VDD or GND 3.3V to 3.6V ⎯⎯500 μA
CPD Power Dissipation Capacitance 3.6V 10 14 pF
I
DDA
(3)
AVDD Power Supply Current AVDD = 3.3V 10 mA
NOTES:
1. For Industrial devices, operating free-air temperature = -40°C to +85°C.
2. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions.
3. For IDD of AVDD, see TYPICAL CHARACTERISTICS.
Min. Max. Unit
Clock frequency 25 140 MHz
fCLOCK Input clock duty cycle 40% 60%
Stabilization time
(2)
1ms
TIMING REQUIREMENTS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND
OPERATING FREE-AIR TEMPERATURE
(1)
NOTES:
1. For Industrial devices, operating free-air temperature = -40°C to +85°C.
2. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase
reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics
table are not applicable.
5
0ºC TO 85ºC TEMPERATURE RANGE
IDTCSP2510C
3.3V PHASE-LOCK LOOP CLOCK DRIVER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C
L = 30pF
(1)
VDD = 3.3V ± 0.3V
Parameter
(2)
From (Input) To (Output) Min. Typ. Max. Unit
tPHASE error 100MHz < CLK < 133MHz FBIN – 150 150 ps
tPHASE error – jitter
(3)
CLK = 133MHz FBIN – 50 50 ps
tSK(o)
(4)
Any Y (133MHz) Any Y ⎯⎯150 ps
Jitter (cycle-cycle) CLK = 133MHz Any Y or FBOUT 75
75 ps
(peak-to-peak)
Duty cycle reference
(5)
CLK = 133MHz Any Y or FBOUT 45 55 %
tR Any Y or FBOUT 0.8 2.1 ns
t
F Any Y or FBOUT 0.8 2.7 ns
NOTES:
1. For Industrial devices, operating free-air temperature = -40°C to +85°C. See PARAMETER MEASUREMENT INFORMATION.
2. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
3. Phase error does not include jitter.
4. The tSK(O) specification is only valid for equal loading of all outputs.
5. See TYPICAL CHARACTERISTICS.
6
0ºC TO 85ºC TEMPERATURE RANGE
IDTCSP2510C
3.3V PHASE-LOCK LOOP CLOCK DRIVER
From Output
Under Test
500
Ω
C
L
=30pF
(2)
Y
CF
FBIN
CLK
CSP2510C
FBOUT
PCBTRACE
CL = 30pF
(2)
500Ω
on each
Y output
CLK
tPHASE ERROR
FBIN
FBOUT
tSK(o)
Any Y
Any Y
tSK(o)
Any Y
Input
Output
or
FBIN
50% V
DD
50% VDD
tR tF
2V
0.4V
3V
0V
2V
0.4V
t
PHASE ERROR
VOL
VOH
PARAMETER MEASUREMENT INFORMATION
(1)
Load Circuit and Voltage Waveforms
Phase ERROR and Skew Calculations
(3,4)
NOTES:
1. All inputs pulses are supplied by generators having the following characteristics: PRR 100MHz ZO = 50Ω, tR 1.2 ns, tF 1.2 ns.
2. CL includes probe and jig capacitance.
3. The outputs are measured one at a time with one transition per measurement.
4. Phase error measurements require equal loading at outputs Y and FBOUT. CF = CL – CFBIN – CPCBTRACE; CFBIN 6pF.

CSP2510CPG

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 10+1 Outputs PLL/Clk Driver
Lifecycle:
New from this manufacturer.
Delivery:
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